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Required Modeling
Job Description
Define the AI core architecture that will shape the next generation of AI chips, leading the global competition in AI computing power. As a key contributor to the competitiveness of AI core architecture, we drive chip architecture innovation starting from algorithm evolution, building a full-stack closed-loop capability of "algorithm-architecture-circuit-system," and creating a globally leading, independently controllable AI accelerator core to support the Ascend AI ecosystem and the implementation of large model strategies.
Responsibilities:
Modeling of HW specification of new architecture and microarchitecture. Working closely with architect and microarchitecture on modeling the specification.

Required Wafer-Scale System: Computation (LLM) and Communication (NoC) Co-Design
In this job opening, we are seeking a highly motivated and visionary researcher to join our team focused on chiplet-based computing systems. This role involves research and development in chiplet-based architectures, aiming to overcome performance and scalability limits of traditional compute platforms.
Responsibilities:
Conduct cutting-edge research on the co-design of communication and computation for wafer-scale systems. On the communication side, the work focuses on architecting Networks-on-Chip, providing scalable, high-bandwidth, and ultra-low-latency interconnects that efficiently span multiple dies and support fine-grained data movement. On the computation side, the research emphasizes optimizing and mapping training and inference workloads to fully exploit wafer-scale resources, improving performance, scalability, and energy efficiency through intelligent task placement and scheduling.
Investigate various aspects of system design, including:
Network-on-Chip design, further including Topology exploration, routing algorithms, and protocol/flow-control design to support high-throughput collective communication, low-latency synchronization, and efficient model/data parallelism
Expressing and Mapping LLM Parallelism to Wafer-Scale System that simplify LLM parallelism (e.g., tensor, pipeline, and data parallelism) and efficiently map training and inference workloads onto wafer-scale system.

We are looking for an architect to work on the invention and development of new SW visible CPU technologies to improve performance of SW scenarios related to memory ordering, memory coherency, multithreading, synchronization, memory safety, caching, etc.
The minimal tasks of this role are:
1. Modeling of new memory related architectural features in the existing CPU performance simulator
2. Development of performance tests or adaptation of existing workloads to be suitable for simulation
3. Conducting performance studies for the workloads of choice either in the performance simulator or on a real chip
4. Develop analysis, conclusions and recommendations based on the above activities
The role can comprehend much more than that depending on the skills, talent and experience of the candidate creating a career path over time. For example, to invent new instructions and mechanisms to overcome significant performance bottlenecks in these areas, refinement and further development of ideas provided by others. Possible participation in development in additional domains
If you want to be part of something bigger, if you are a team player with excellent communication skills and motivation to revolutionize data-center technology, youre welcome on board!

We are looking for a talented and motivated M.Sc. or Ph.D. student to join our Systems Research team and contribute to advanced research in next-generation computing systems.
In this role, you will:
Participate in research and analysis of state-of-the-art computer systems and emerging technologies.
Investigate system performance, identify bottlenecks, and explore innovative approaches for improving system efficiency, scalability, and performance.
Develop and evaluate Proof-of-Concepts (PoCs) for end-to-end systems and novel architectures for data centers, including AI, Cloud, Storage, Big Data, and distributed computing.
Gain hands-on experience in implementing, testing, benchmarking, and validating new system concepts and architectures.
Work closely with experienced researchers, architects, and engineers on advanced research and development projects.
Explore recent academic research and emerging technologies, identify new research opportunities, and contribute ideas and insights to ongoing research activities.

Required Senior Firmware Developer
Our team at the Huawei Smart Platforms innovation Lab is chartered to research and incubate new technologies that will redefine the future data centers, cloud and supercomputer performance and functionality.
What will you be doing?
The group is looking to hire a deeply technical and creative developer to design and prototype end-to-end novel solutions in the networking and distributed computing domains for our data center, covering Cloud, Storage Big Data, network programmability, and end-to-end network software stacks.
This position offers the opportunity to have a real impact in a research-focused team in a dynamic company.
If you are a team player with excellent communication skills and motivation to revolutionize the cloud, you are welcome on board!