We are looking for an experienced architect with deep technical expertise in high-speed SERDES interfaces and extensive experience working with IEEE standards such as 802.3 (including subgroups like 802.3ck and 802.3cw).
The ideal candidate will have a background in various generations of Ethernet technologies, including lower speeds from prior generations (e.g., 100G, 200G) and will play a pivotal role in pushing the boundaries of high-speed data transmission, aiming to achieve 448Gb lane speeds and beyond.
This role will involve conducting in-depth research, driving industry standardization efforts, and collaborating closely with industry partners and peers to spearhead technological advancements.
Requirements: 5+ years of experience in high-speed SERDES design, implementation, or research, with hands-on involvement in previous generations of Ethernet standards (e.g., 100G, 200G, 400G).
Proven experience with IEEE 802.3 working groups and standards, particularly in areas related to Ethernet and optical PHY layer technologies (e.g., 802.3ba, 802.3bs, 802.3cd, 802.3ck)
Deep knowledge of modulation techniques such as PAM4 and NRZ, as well as high-speed signaling protocols used in both optical and copper interconnects
Expertise in physical layer research, signal integrity, channel modeling, equalization and error correction techniques for high-speed links
Experience working with key industry players, vendors, and consortiums to shape standards and drive technology adoption
Strong ability to produce technical reports, white papers, and presentations that distill complex technical information into actionable insights
How would you stand out:
Advanced Degree: Masters or PhD in Electrical Engineering, Communications Engineering, or a related field
Expertise and knowledge in in PCS/PMA sublayers, GMII Interface and MAC (Media Access control) in IEEE 802.3.
Extensive involvement in developing Ethernet standards from 100G up to 400G, with insights into the evolution toward 800G and Terabit Ethernet
Demonstrated leadership in managing cross-functional engineering projects related to PHY layer technologies and SERDES interface innovation
Previous experience presenting at or contributing to major industry conferences and events (e.g., OFC, ECOC, IEEE Ethernet Alliance meetings).
This position is open to all candidates.