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You'll be joining our Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.
You will be leveraging your backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

As a Senior Platform Engineer you will help deliver a smooth and consistent developer experience to our product/AI teams. This enables them to iterate quickly and deliver products faster to the market. The team aims to streamline development processes, reduce friction and provide developers with the right tools and infrastructure to build high-quality software efficiently which effectively aligns technical execution with our business objectives. Our techstack includes AWS, Python, RDS, EKS, ECS, RMQ and Redis.

You will:
You will have a direct impact on devs' daily smile :) , by focusing on their Devex and velocity through implementing and providing easy and intuitive self serve tools

Lead the design and implementation of infrastructure of complex, time-critical microservices systems, collaborating with AI, data, and product teams to ensure high-quality code using latest technologies while maintaining high developer velocity.

Drive improvements to backend infrastructure, focusing on scalability, reliability, and performance to enhance the daily experience and productivity of developers, including implementing intuitive self-serve tools.

Contribute to defining and realizing the technology vision of the company, evaluating and integrating new technologies to enhance platform capabilities including Gen AI, and troubleshooting complex issues to ensure platform performance and availability. Proactively establish and maintain CI/CD practices and processes including hybrid envs.

Enhance system scalability, performance, and reliability.
What success looks like:

Leading the design and implementation of infrastructure for complex microservices systems, ensuring high-quality code, and maintaining a high pace of development while collaborating effectively with other teams.

Driving improvements to the backend infrastructure, focusing on scalability, reliability, and performance to enhance the daily experience and productivity of developers.

Contributing to the company's technology vision by evaluating and integrating new technologies, including Gen AI, and troubleshooting complex issues to ensure platform performance and availability.

Working closely with development teams to support architecture best practices and enhance system scalability, performance, and reliability.

Mentoring and advising other team members in code review, performance, scalability, and more.

Demonstrating excellent communication and collaboration skills, and being a team player with a highly motivated, can-do approach.

As a Senior DevOps Engineer youll own all the aspects of our cloud infrastructure, in terms of availability, security, scale, costs, DevEx and more.

This role is critical to building efficient practices that empower our teams to deliver high-quality products quickly and effectively, ensuring technical execution stays aligned with our business objectives.

Our stack includes AWS, Kubernetes, Terraform, Helm, Python, Prometheus, GitHub Actions and more.

We are looking for a Senior Algorithm Developer with experience in NLP and LLMs, who is highly motivated, collaborative, and results-driven individual who can work both independently and as part of a multidisciplinary team. The ideal candidate has a strong can-do attitude, excellent problem-solving skills, and a passion for leveraging AI to solve meaningful challenges in text analysis in the medical domain.

As part of the AI team you will:

Design, develop, implement, and evaluate robust, scalable AI algorithms and agentic workflows tailored to real-world challenges in clinical settings.

Prepare, process, and analyze complex medical data to support algorithm development and validation.

Ensure the reliability, performance, and accuracy of algorithms in production, including troubleshooting, testing, monitoring, and continuous improvement.

Collaborate closely with Product Managers and Clinical Specialists to translate clinical and business needs into data-driven solutions.

Research, develop and integrate cutting-edge text based alogirthms on medical text.

Apply NLP and Large Language Models (LLMs) to extract insights from medical texts and develop intelligent agents for optimized clinical decision support.

Stay up to date with cutting-edge advancements in GenAI, LLMs, and Deep Learning.

Organize and actively participate in seminars, book clubs, and conferences.

Main Technical Stack:

NLP/LLMs: Pydantic, Hugging Face Transformers, spaCy, Amazon Bedrock

Infrastructure: AWS, Docker

Programming Languages: Python

Deep Learning Frameworks: TensorFlow, Keras, Pytorch

we are looking for a ASIC Leader.
Your Impact:
Review micro-architecture specifications
Supervise verification team members and provide professional guidanc
Implement Verification environment UVM based
Collaborate with Design engineers to resolve bugs and achieve coverage closure
Work with the firmware/Lab teams to verify chip flows
Perform debug, root-cause analysis, and post-silicon validation in the lab

Youll be joining the post silicon validation team in PHY system group as part of the silicon development .
Our team deals with PHY and system aspects of the SerDes communication IP: PHY FW, calibrations, system definitions and operations and post-silicon validation including developing the automation infrastructure and tools.
We use latest silicon technologies and processes to build the largest scale and most complex devices at the edge of feasibility.

we are looking for a ASIC Design Engineering Technical Leader.
Your Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab

we are looking for a Logic Design Engineer.
Your Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab

we are looking for a Junior Physical Design Engineer.
You'll be joining our Physical Design team , which is at the center of the silicon development . Our engineers deal with all chip design aspects: definition, architecture, micro-architecture, design, verification, signoff and validation.
We use the latest silicon technologies and processes to build the largest scale and most complex devices at the edge of feasibility.

we are looking for a Senior Physical Design Engineer.
Your Impact:
You'll be part of the team, which is at the heart of software and ASIC design efforts.
You'll handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

we are looking for a Senior Asic Design.
Your Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab

we are looking for a IC Package Design Engineer.
In this role, you will contribute to the development of complex ASIC package designs from early planning and exploration through implementation and tapeout. You will collaborate across package design, layout, SI/PI, and silicon teams to help deliver high‑speed, robust, and manufacturable package solutions.
You will participate in package architecture activities, design tradeoff discussions, and technical problem solving while growing your expertise in advanced packaging technologies and system-level integration. This role provides an opportunity to work on some of the most advanced networking silicon products in the industry within a highly collaborative engineering environment.
Responsibilities:
As a member of the Package Design team, you will:
Lead the package design activities including planning, floorplanning, pinout optimization, stack‑up definition, and high‑speed routing suport.
Collaborate with SI/PI, silicon floorplanning, layout, and manufacturing teams to ensure high‑quality package solutions.
Support package implementation activities and work closely with layout designers to ensure alignment between design intent and physical implementation.
Participate in technical investigations, design reviews, and tradeoff discussions involving performance, manufacturability, and schedule considerations.
Assist in developing and improving package design methodologies, flows, and best practices.
Contribute to debugging, issue resolution, and package bring‑up activities as needed.

We are excited to announce that the team is undergoing rapid growth, and we are looking for a C++ Software Developer.
Your Impact:
Craft and develop software driving the world's most complex infrastructures
Gain intimate knowledge of world-class silicon and programming models
Work with architecture and design teams to define the next generation of ASIC products being developed

we are looking for a ASIC Engineer.
Your Impact:
Review micro-architecture specifications
Implement Verification environment UVM based
Collaborate with Design engineers to resolve bugs and achieve coverage closure
Work with the firmware/Lab teams to verify chip flows
Perform debug, root-cause analysis, and post-silicon validation in the lab