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About Cardo Cardo Systems is a provider of cutting-edge communication and connectivity devices and applications for powersports and outdoor enthusiasts. In 2026, Cardo is proudly unveiling its Beyond Helmet line, the first of its kind in the motorcycle industry, fostering a new age in safety, sound, and communications. After pioneering the world’s first Bluetooth-based wireless intercom headset in 2004, Cardo has been responsible for many of the industry’s innovations, revolutionizing communication, pushing technological boundaries, and enhancing user safety. Now sold in over 100 countries, Cardo is proud to be the world’s leading communication device for groups in motion. ?Cardo Systems is looking for a Junior Hardware Engineer to join our ATE team and play a key role in the design, development, and integration of advanced test equipment for our cutting-edge multidisciplinary products. In this role, you will be involved in hardware board design, validation, testing, and production support while working across a wide range of technologies including analog, digital, audio, RF, and optical systems. You will collaborate closely with Hardware, Firmware, Manufacturing, and Quality teams to ensure reliable and efficient testing solutions throughout the product lifecycle. Responsibilities:
* Design and develop ATE (Automated Test Equipment) hardware boards and test systems.
* Integrate and validate multidisciplinary technologies including analog, digital, audio, RF, optics, and power circuits.
* Work with microcontrollers and embedded hardware platforms.
* Develop test specifications, test methodologies, and validation procedures.
* Support production activities, troubleshooting, and continuous improvement of manufacturing test processes.
* Perform hardware bring-up, debugging, and characterization using lab equipment.
* Collaborate with cross-functional teams throughout development and production stages.
* Operate effectively in an AI-driven engineering environment.

Review micro-architecture specifications

Supervise verification team members and provide professional guidance

Implement Verification environment UVM based

Collaborate with Design engineers to resolve bugs and achieve coverage closure

Work with the firmware/Lab teams to verify chip flows

Perform debug, root-cause analysis, and post-silicon validation in the lab

Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab

We are looking for an experienced Design Verification engineer to join our DFT team and help establish and grow DFT DV activity in the Cisco SiliconOne DFT team. This role is relevant for engineers with experience in DV roles, either in DFT DV or in other verification domains, who are interested in becoming familiar with DFT design, verification methodologies, and the challenges of validating testability features in advanced silicon.

Your Impact
Lead and drive DFT verification activities within the Cisco SiliconOne DFT team.

Develop verification plans, environments, checkers, assertions, and coverage models for DFT features.

Verify DFT architecture and implementation in close collaboration with DFT, design, architecture, and verification teams.

Work on verification of scan, MBIST, IJTAG/JTAG, test access mechanisms, DFT controllers, and related SoC-level test features.

Debug complex pre-silicon issues across RTL, verification environments, and DFT logic.

Contribute to scalable methodologies, reusable verification components, and best practices for DFT DV.

Help bridge between general DV methodologies and DFT-specific design and verification needs.

As a Project Manager, you will support multiple ASIC development programs by coordinating execution, tracking deliverables, and enabling collaboration across engineering teams. You will strengthen operational excellence through AI-based automation and tracking solutions. Your work will help teams identify risks and dependencies early, maintain alignment, and deliver programs successfully.

Support Program Managers throughout each phase of ASIC program execution.
Track milestones, action items, dependencies, risks, deliverables, status reports, dashboards, and execution metrics across multiple projects.
Coordinate activities among ASIC, Software, and Business Operations teams, including global stakeholders.
Drive follow-up and accountability to ensure project actions are completed on time.
Develop AI-powered tracking tools and automation solutions that improve project visibility, streamline processes, and strengthen program management methodologies.
Collaborate with engineering and operations teams to maintain alignment and support successful program delivery.

We are excited to announce that the Cisco Silicon One team is undergoing rapid growth, and we are looking for a Senior C++ Software Developer.

Your Impact

Craft and develop software driving the world's most complex infrastructures
Gain intimate knowledge of world-class silicon and programming models
Work with architecture and design teams to define the next generation of ASIC products being developed

In this role, you will contribute to the development of complex ASIC package designs from early planning and exploration through implementation and tapeout. You will collaborate across package design, layout, SI/PI, and silicon teams to help deliver high‑speed, robust, and manufacturable package solutions.

You will participate in package architecture activities, design tradeoff discussions, and technical problem solving while growing your expertise in advanced packaging technologies and system-level integration. This role provides an opportunity to work on some of the most advanced networking silicon products in the industry within a highly collaborative engineering environment.

Responsibilities:
As a member of the Package Design team, you will:

Lead the package design activities including planning, floorplanning, pinout optimization, stack‑up definition, and high‑speed routing support.

Collaborate with SI/PI, silicon floorplanning, layout, and manufacturing teams to ensure high‑quality package solutions.

Support package implementation activities and work closely with layout designers to ensure alignment between design intent and physical implementation.

Participate in technical investigations, design reviews, and tradeoff discussions involving performance, manufacturability, and schedule considerations.

Assist in developing and improving package design methodologies, flows, and best practices.

Contribute to debugging, issue resolution, and package bring‑up activities as needed.

As a Software Engineering Technical Leader, you will drive the technical vision and execution for complex security policy and access solutions that safeguard enterprise networks globally. You will leverage your deep expertise in systems programming using C, C++, and Java to architect and develop robust, scalable software. By providing technical leadership, you will mentor peers, guide architectural decisions, and foster a culture of innovation and continuous improvement within the team. Your work will directly contribute to Cisco's mission by ensuring our network access solutions are secure, programmable, and highly reliable. You will also champion software programmability and integrate automation and orchestration practices to streamline development and enhance product performance, ultimately empowering our customers to connect with confidence.

We are seeking a talented and driven Senior Software Verification Engineer to join our innovative team and tackle SW verification challenges in the domains of high-speed networking, virtualization, and security. You will play a key role in validating and testing complex software products that support Ethernet and InfiniBand protocols, delivering advanced networking, storage, and security services for cloud, compute, and AI workloads.

What Youll Be Doing:

Develop and Automate Testing: Design, implement, and maintain automated test scripts and frameworks (primarily in Python) to verify the correct functionality of our software products.

End-to-End Feature Ownership: Deep dive into feature sets, taking responsibility from test planning through to final implementation and full automation.

System & Integration Validation: Validate software functionality and performance through system-level and integration testing, utilizing Linux-based environments and virtualization tools.

Test Environment Management: Set up, maintain, and optimize test environments using Linux, Docker, virtual machines, and other modern tools.

Collaboration & Communication: Work closely with software, DevOps, architecture, and product teams to define test requirements, coordinate releases, and ensure high-quality product delivery.

Continuous Improvement: Drive design verification flows, contribute to methodology improvements, and leverage planning/tracking systems to manage release progress and build release indicators.

Defect Analysis: Analyze test results, file defects, and track issues to closure, ensuring robust and scalable solutions.

The team leads the development of networking infrastructure for NVIDIA's next-generation data centers, focusing on accelerated performance while enabling optimized end-to-end GPU connectivity, focusing on datacenter-level optimized solutions for AI.

As a leader of our switch Hardware Engineering team, you'll guide, encourage, and drive a team of highly skilled hardware engineers, providing them with stimulating and ambitious assignments and enabling them to stay creative and motivated while delivering products on schedule.

What You'll Be Doing:

Build the best team to design and execute high-performance switch system from concept to mass production.

Be a key member of the technical leadership team developing world-class switch designs.

This position is hands-on and will require a deep understanding of all technical/engineering aspects of the project with intimate familiarity with the entire development flow. From a technical standpoint, you will lead and support engineering teams in the following areas: specification definition, electrical schematics, opto-mechanical design, component selection, layout guidance, hands-on lab testing, production processes, qualification workflows, micro-architecture development, verification, characterization, design for testability, cost optimization, reliability, and more.

Collaborate with and integrate all HW project disciplines: Board Design, Assembly Process, Mechanics, Thermal, PCB Layout, Process , Production Engineering, Software/Firmware, Procurement, NPI, and more.

Plan and oversee your teams work on multiple simultaneous development projects in coordination with the broader leadership team. Manage direct reports, set goals, provide coaching, conduct performance appraisals, plan careers, and make compensation recommendations.

Collect, examine, and filter requirements from internal customers such as marketing, software, and systems engineering to assemble a comprehensive plan of record for next-generation switches while planning resource allocation for projects and assign team members effectively.

Schedule projects, create realistic outcome estimates, and drive timely, successful execution for high-volume manufacturing.

Lead hands-on lab debugging to fix complex silicon performance, characterization, and yield issues. Use bench findings and board-probing data to give feedback directly to the architecture and design teams. Lead ASIC bring-up on validation boards, focusing heavily on SerDes, high-speed interfaces, and power/clock domains. Run characterization across PVT (Process, Voltage, Temperature) conditions and analyse large datasets to resolve performance bottlenecks and improve chip yield. Write and optimize clean Python code to automate lab equipment and test internal chip logic. Serve as the technical lead for complex hardware debug, defining validation methodologies, and advanced lab measurement techniques for the team.

You will work on physical synthesis, place and route, optimization, timing closure, and floor planning activities. Success in this role means delivering high-quality implementation results, learning quickly from senior engineers, and helping improve the flow and methodology used by the team.

Contribute to physical synthesis, place and route, optimization, and timing closure for complex VLSI designs.
Support design floor planning and implementation planning in collaboration with senior physical design engineers.
Analyze timing, congestion, power, area, and design-rule issues and help drive them toward closure.
Work with physical design verification flows, including LVS and DRC, to support clean implementation handoff.
Partner with cross-functional teams to debug implementation issues and improve backend flow quality.

Our HW team in Israel is looking for an experienced system/board designer to join the Hardware Switch Group. The team leads the development of networking infrastructure for our next-generation data centers focusing on accelerated performance while enabling optimized end to end GPU connectivity.

What you'll be doing:

Perform board bring-up, hardware validation, characterization, and system-level debugging in the lab.

Debug issues involving power, signal integrity, interfaces, components, firmware interactions, and system behavior.

Support productization, production-line stabilization, and hardware-related issues during mass production.

Read and analyze schematics, PCB layouts, component specifications, design documentation, and manufacturing data.

Define test strategies, develop validation plans, execute test procedures, and improve coverage and efficiency.

Collaborate closely with electrical, mechanical, thermal, firmware, software, system, manufacturing, and quality teams throughout the product lifecycle.

Provide technical leadership and hands-on support for critical hardware issues.

Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab