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We are expanding our System Integration & Validation group and invite you to explore Space with us and join our group of experts.



Job Description:

Define Integrations and integration testing requirements based on product requirements and technical system specifications.

Define the system integration approach and system integration tests for multidisciplinary projects and applications.

Develop and Design test cases and tools for integration and validation.

Plan, implement and conduct system tests based on test plans.

Debug of hardware and software embedded systems.

Create detailed integration & test reports.

Hands-on in various lab set-ups (analog, digital, software, Firmware).

We are looking for Analog Layout Engineer
About The Position
We are a fast-growing startup developing cutting-edge hardware infrastructure for blockchain and cloud-privacy applications.
Our team takes products from ASIC definition, planning, and implementation all the way through production and deployment in multi-ASIC operational systems.
With a multidisciplinary team boasting decades of experience in developing and manufacturing high-end ASIC products, we set the highest standards for performance, efficiency, and quality.
Roles and responsibilities:
Layout design of sensitive analog circuits where you will need to bring state-of-the-art solutions.
In close co-operation with the Circuit Designer, review and analyze complex analog schematics for layout implementation.
Ensures layout designs best functionality and quality by performing all relevant checks like parasitic checks, IR drop and Electromigration, noise and DFM.
Perform post-layout iterations to ensure the best results.

Required Physical Design Engineer
About The Position:
We design and builds hardware that fuels disruptive blockchain technologies by accelerating compute performance. Our world-class teams are transforming the future of data, creating the infrastructure that will power the next generation of secure, scalable, green computing. The main bottleneck in scaling cutting-edge solutions in privacy tech, data analysis, and real-time computing is acceleration existing hardware cannot keep up with data processing needs. Our products reshape how data is processed and used on a global scale, and were looking for the brightest people to join us. We are seeking talented and driven individuals to become part of our Yoqneam IC team.
Responsibilities:
Floor Planning Top to Bottom & Bottom up Block level. Exploring different floorplan structures to achieve both the best area & ease of convergence.
Generate high-quality PnR results for one or more digital blocks by applying engineering best practices.
Optimize designs based on key metrics, including power, area, and performance trade-off analyses.
Drive sign-off timing convergence for high-performance designs at the block level, including DRC and LVS signoff
Analyze power integrity (EMIR) results of blocks and apply corrective measures to resolve identified issues.
Collaborating closely with frontend, verification, architecture, physical design, and analog teams.
Work closely with EDA (Electronic Design Automation) vendors on the latest tool feature development and qualification.

We are looking for a Validation and Verification (V&V) Engineer to join our team and play a key role in system testing for multidisciplinary IoT products within our Water Management Ecosystem.
Main Responsibilities:
● Designing a testing strategy, creating test plans based on system requirements
● Writing tests ready for automation
● Testing electrical, functional, communication, and integration aspects of a product throughout its life cycle
● Writing test reports, Fault documentation, verification of resolved issues,
● Participating actively in integration activities and complex failure analysis
● Working closely with the departments of Software, Firmware, Hardware, and Mechanical Engineering as well as System Engineering

We are leading the way in groundbreaking developments in Artificial Intelligence, High-Performance Computing and Visualization. The GPU, our invention, serves as the visual cortex of modern computers and is at the heart of our products and services. Our work opens up new universes to explore, enables outstanding creativity and discovery, and powers what were once science fiction inventions from artificial intelligence to autonomous cars. We are looking for excellent people like you to help us accelerate the next wave of artificial intelligence.

We are looking for a skilled, creative, and highly motivated Senior PHY System Engineer to join the End-to-End (E2E) physical-layer performance team, as part of the Post-silicon department

What youll be doing:

End-to-End responsibility on the link level performance characterization, verification, and debugging.

Debugging of link issues of NVIDIA systems, while diving into the product HW design and SW/FW operation.

Characterizing optical and electrical performance using lab equipment and SW tools.

Take an active part in silicon bring-up while managing E2E testing of newest ASICs, with the objective of driving product to mass production with first-in-class performance.

Characterizing products performance using lab equipment, such as oscilloscope, Spectrum/Network analyzer, Pattern-generator, etc.

Working in front of various test teams, with the responsibility of addressing issues and monitoring the test flows conducted by them

Leading data-driven discussions about the product functionality and areas for improvement.

Testing NVIDIA Electro-Optical and Electrical chips and systems.

Defining testing requirements for new products based on electrical and optical specifications.