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we are looking for a 100% hands-on network software engineer to join the block Storage group. you will be a member of a team that builds the next generation block Storage capabilities. you will work closely with a variety of teams and architects including the networking team, and external customers. you will take part in defining the software architecture and implementation of the most advanced Storage services! services that will need to meet extreme performance and scalability demands! we have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform of tomorrow.
at our company, we work, think and learn as a team. we thrive in a deeply strong environment, and we're passionate about a culture that demands innovation and the highest standards. the rewards are sweet and include collaborating with some of the smartest people in the industry, an aggressive compensation plan that rewards top performers, and the opportunity to work on products that transform the way people work and play.
what youll be doing:
100% hands-on coding role in C language, Kernel and userspace
research, design, implement and TEST, new and existing, advance networking service and features of our block Storage solution, in both host and dpu environments.
acquire understanding of the algorithms, the technicalities and the interaction with other components across our block Storage ecosystem.
analyze and solve challenging bugs and customer cases in large scale production systems, identifying issues in our or inbox Kernel modules and often in other components. drive new solutions based on any issues that arise

our team in israel is looking for a dedicated chiplet sta owner to join us in defining the next era of ai's networking. this is an outstanding opportunity to work with innovative technology and collaborate with some of the most experienced minds in the industry. if you are ambitious, passionate about flawless design, and eager to make a lasting impact, this role is perfect for you!
what you'll be doing:
perform advanced static timing analysis (sta) at chiplet and fc level.
running prime time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation.
identify convergence risks and work closely with physical design, rtl and dft teams, ensuring convergence throughout various project stages.
responsible for a full timing closer and quality approval from pre-layout sta model through signoff.

we are now looking for a senior chip design rtl design engineer for the switch silicon group.
as a chip design engineer at nvidia's networking business unit, you'll join a group of passionate engineers to design and implement the next generation state of the art switch silicon chips. in this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
what you'll be doing:
work in a combined design and verification team which develops some of the switch silicon core units.
plan and design rtl units / blocks according to arch & micro arch specifications under challenging constraints with high orientation to power, area, and performance.
build reference models, verify and simulate chip blocks/entities according to specifications.
work closely with multiple teams within organizations such as architecture, micro- architecture, and fw.

we are looking for a power u-arch senior engineer. our company is known as a world leader in providing energy-efficient high-performance products and we continue to invest in the research and development of hyper-efficient SOC architectures. we are continually innovating in creative and unrivaled ways to improve our ability to deliver exceptional perf/watt solutions in a wide range of sectors and verticals. come join our applied power team to develop state of the art dpu products.
what you'll be doing:
lead a micro-architecture of power features such as: power management, logical power features, etc
work with dpu arch team on power features definition.
understand the workload characteristics for dpu workloads at system scale to drive new hw/sw features.

we are looking for an excellent software engineer for the switch sdk group. you will join the sdk group and take our product to next level, working closely with various other design and architecture teams and gain a deep understanding of our products and technologies. our company has been transforming computer graphics, pc gaming, and accelerated computing for more than 25 years. its a unique legacy of innovation thats fueled by great technology-and amazing people.
today, were tapping into the unlimited potential of ai to define the next era of computing. an era in which our gpu acts as the brains of computers, robots, and self-driving cars that can understand the world. doing whats never been done before takes vision, innovation, and the worlds best talent. as an employee, youll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. come join the team and see how you can make a lasting impact on the world.
what youll be doing:
design, develop, optimize and maintain apis, tools and libraries for switching, routing, analytics, telemetry and many other modules
collaborate with team members, architects, QA teams, and customers (both external and internal)
innovate & rapidly develop poc prototypes that can then be developed into full-fledged products/solutions

we are looking for an outstanding senior technical instructor to join our education services team. in this role, you will provide advanced training on nvidias data center, ai, and hpc platforms to customers and partners around the world. you will also contribute to developing training content, including presentation decks, hands-on manuals, and supporting materials. you will help engineers, architects, and operations teams build the skills needed to design, deploy, and operate our company -powered ai data centers with confidence. as part of this, you will take part in the design of hands-on workshops and lab environments that simulate real systems and data center components, enabling learners to practice on realistic end-to-end scenarios. 
what youll be doing:
deliver in-person and remote technical training on our data center, ai, and hpc platforms for customers and partners, with up to 25% travel as needed.
lead lab-based training sessions that walk learners through end-to-end workflows on our gpus, dgx/gb200 systems, high-speed networking, and ai/hpc software stacks.
collaborate with internal experts and content developers to build agendas, exercises, and demos that reflect real customer use cases and guidelines.
serve as a subject-matter guide (sme) for a dedicated production team and learning developers. they build primary content. partner with them on slideware, lab guides, videos, simulations, visual demos, and exercises. ensure technical accuracy and realism.
act as a technical ambassador for our company in front of partner and customer audiences, answering inquiries, facilitating discussions, and guiding learners through fix and what-if scenarios.

our company is searching for a strong technical leader to own the backbone of our networking research capabilities. we are looking for an engineering manager to lead the development of our high-fidelity network simulation platform and the extensive on-premise infrastructure that powers it.
in this role, you will lead a team of performance simulation software engineers and DevOps /infrastructure specialists. you will own the "simulation-as-a-service" product-a critical platform used by internal researchers to model next-generation data center architectures. your mission is to ensure our simulations are accurate, performant, and accessible, while managing the large-scale compute clusters required to run them.
what you'll be doing:
team leadership: manage and mentor a team of C ++ software engineers and DevOps infrastructure engineers, fostering a culture of performance, reliability, and code quality.
product ownership (sim-as-a-service): treat the internal simulation platform as a product. work with research partners to define the roadmap, prioritize features, and ensure high availability for users.
high-performance simulation: be responsible for the architecture and optimization of complex network simulation engines ( C ++ based), ensuring they can scale to model extensive data center topologies with high fidelity.
infrastructure management: own the lifecycle of our on-premise compute clusters and servers. drive decisions on hardware upgrades, prioritisation, and managing system resources.
DevOps & automation: lead the strategy for ci/cd pipelines, automated testing, and containerized deployments to ensure rapid iteration and stability of the simulation platform.
multi-functional collaboration: partner with the ai agents team to expose simulation apis, enabling agents to run experiments and gather data autonomously.

we are looking for an experienced dft engineer to join an exceptional team of dft experts to develop the next generation dft technologies.
as a dft engineer at the networking group at our company, you will participate in definition and implementation of our dft technologies in various projects. this position offers the opportunity to have real impact in a dynamic, technology-focused company impacting switches, nic and SOC product lines. we are working closely with a wide range of aspects - chip design, backend, verification and production testing. we are working on the most advanced technologies and sophisticated products, our dft solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.
what you'll be doing:
in this position, you will be responsible for defining, coding and integrating sophisticated dft components into various projects and using state-of-the-art technologies.
as a member of our dft design team, you will participate in defining various dft features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.
strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.

looking for outstanding chip design Verification engineers to join our networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
come and take a significant part in designing and verifying our ground-breaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.
what you will be doing:
work in a combined design and verification team which develops core units within the networking silicon.
build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.
work closely with multiple teams within organizations such as architecture, micro- architecture, full-chip, fw and post-silicon validation.
your daily work will involve all aspects of design verification: planning, coding, coverage and integration

our company networking unit is a world-leader fast-growing company which supports the most powerful supercomputers in the world. we make outstanding artificial intelligence happen and accelerate open-ais chat-gpt, for example. we believe in our people and products and seek excellent people to join us!
we're looking for a hardware u/architect for our switch division. in this position, as part of a small (~10 employees) elite team, you will have the chance to define the architecture of our next generation switch product lines performance, both ethernet and infiniband. your role will be cross-disciplinary, working with software, asic design, verification, physical design and platform teams to improve performance and debug.
what you'll be doing:
learn and understand the switch u/architecture thoroughly across all aspects and become a source of information for the design and Verification engineers.
define the implementation of the most sophisticated performance features of our next products, balancing architecture requirements with backend, execution, and design considerations.
define the implementation of debug capabilities to support performance validation and improvements
understand our system requirement and help define the por of our switch product line.
face the most challenging full-chip correctness and performance issues, which cannot be handled by the units designers as they require full cross-unit understanding of the chip.
work closely with board and package design to understand the different design limitations: power, di/dt, temperature, signal-integrity etc.
thoroughly understand ethernet, infiniband and nvlink protocols.

our company has evolved ai infrastructure by merging gpu virtualization with kubernetes-native capabilities. our world class ai platform allows organizations to improve productivity and efficiency for data scientists and Machine Learning engineers. with deep kubernetes expertise and a focus on innovation, we are dedicated to developing cutting-edge technologies, delivering the best User Experience for our customers, and providing deep visibility into workload performance through rich metrics that help users optimize their ai workloads. we are looking for highly skilled software engineers to join our platform group and help shape the future of ai infrastructure.
the role of a senior software engineer in the platform group is to design and develop scalable, high-performance systems that support the next generation of ai workloads. you will collaborate with experts across domains, tackle complex challenges, and drive innovations that empower our users to push the limits of ai capabilities.
what youll be doing:
designing and developing enterprise-grade systems with a strong focus on scalability, reliability, and performance.
building and optimizing microservices-based architectures using kubernetes and cloud-native technologies.
collaborating closely with backend engineers, product managers, and other collaborators to deliver impactful solutions.
writing clean, maintainable, and testable code in go
conducting code and design reviews to uphold high-quality standards and mentor team members.

we're looking for a senior software engineer to stand at the forefront of ai innovation in this space. if you're an ai-savvy builder who's ready for the unique and tantalizing challenges of modern vlsi software development, this role is for you!
what you'll be doing:
as our lead AI Engineer, you'll work side-by-side with senior staff to develop systems for a broad range of applications, from data collection and analysis to mcp servers and agentic workflows over our powerful in-house orchestration apis. you'll use nvidia's abundant cloud compute to research and deploy any resources those systems need, take part in critical decisions about which technologies to employ, and assume senior duties in mentoring, code review, and instruction initiatives for the entire team.
innovation and a startup mentality tempered by quality and maintainability standards are in the team's dna. valuable ideas from anyone - junior or senior, newcomer or veteran - are rewarded with the time and creative freedom to bring the vision to life. come build with us!

you'll be responsible for developing architectures, algorithms, models, and methodologies aimed to improve the power consumption of our dpu and nic products.
play a key role in facing these challenges and lead the research of innovative power techniques and power modeling that will drive our solutions to the next level.
take an active part in hw design reviews