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In this role, you will be responsible for several teams of architects, engineers and software developers, all working together to conduct state-of-the-art R&D in system and network architecture. As the group lead, you will guide and mentor the individual team leads, and also conduct hands-on work leading architecture, technology innovation and technical planning and of high-performance computing cluster network, which oriented at AI, HPC, and big data.

Responsibilities
You will perform a wide range of duties including:
Architecture Innovation:
Deeply analyzing the advantages and disadvantages of mainstream network systems, to find opportunities for network architecture innovation;
Insight into the technology developing trend of the high-performance computing network field, and leading the corresponding technology planning.
Exploring new architectures of high-performance computing network systems and efficiently integrating communication library, topology, and network protocol to solve performance bottlenecks.
Technical breakthroughs in networking and cluster routing algorithm：
Analyzes computing cluster network performance and leads the development of computing cluster network technologies
Research and optimize the heterogeneous interconnection topology of key computing chips to continuously improve the key competitiveness of Huawei computing heterogeneous chipsets.
Responsible for the research of data center network technologies, and guide network topology design and routing algorithm development
Group leadership:
Lead the development of a comprehensive system architecture for AI Fabric and HPC Fabric solutions.
Manage and mentor highly skilled team leaders, to ensure that the group operates together in pursuit of common goal.
Foster a collaborative and innovative work environment.
Provide technical guidance and support to team members.
Collaborate closely with cross-functional teams internationally, including hardware, software, and ucode design teams, to ensure alignment of architectural decisions with product and platform common objectives.
Initiate and supervise collaborations with top academic researchers in Israel and abroad.
Stay up to date with emerging technologies and industry trends in AI, HPC and big data industries.
Evaluate and recommend technologies and next generation projects.
Occasional travel related to ongoing projects, seminars, conferences etc.

We are seeking a Senior System Management Architect to lead the management architecture for our advanced SmartNIC cards. You will be the resident expert for SmartNIC system management, ensuring that NIC ASICs, Baseboard Management Controllers (BMCs), MCUs, CPUs, and CPLDs operate in perfect unison. You will own the lifecycle management specifications for SmartNIC platforms-from factory provisioning and day-one deployment to complex orchestrated reset flows and secure recovery. If you are someone who enjoys looking at a high-level system diagram and then immediately diving into the I2C/I3C bus topologies and PLDM command structures required to make it work, this role is for you.

What you'll be doing:

System Architecture & Flow Definition: Define and document comprehensive production, provisioning, update, recovery and reset flows for SmartNIC cards. Crucially, you will ensure that these board-level architectural decisions perfectly align with and support overarching platform-level needs, orchestrating seamless coordination between the NIC ASIC, BMC, CPU, and peripheral components.

Security & Provisioning: Specify security provisioning flows including OTP fusing, secure boot enablement, attestation key injection, certificate chain management, RPMC key derivation, and PQC (Post-Quantum Cryptography) requirements. Define IPN-to-OPN transition and component locking procedures.

Protocol Implementation & Guidance: Specify the use of standard management protocols (MCTP, PLDM, SPDM, NC-SI) across internal board interfaces to achieve secure boot, firmware updates, and telemetry gathering.

Hardware/Software Intersect: Dive deep into device-level hardware and software behaviour. Define CPLD logic requirements, power-sequencing dependencies, and reset orchestration (e.g., handling PCIe PERST#, SBR, and forced resets) for multi-host and standalone SmartNIC environments.

Interface Management: Architect intra-board communication pathways using PCIe, I2C/I3C, USB, and SPI, ensuring robust out-of-band (OOB) and in-band management connectivity.

Cross-Functional Leadership: Collaborate tightly with Production teams, Hardware and Firmware Engineering, NIC FW/Driver teams, and QA to translate your architectural specifications into implementable, testable realities.

Technical Documentation: Author rigorous technical specifications, test plans, and architectural design documents to guide both development and factory production.

We are looking for a proactive and detail-oriented Communications & Media Relations Lead to support the execution of PR and communications strategy. Reporting to the Director of PR & Communications, this role will play a key part in driving media engagement, amplifying our brand presence, and supporting storytelling efforts across multiple internal and external channels.

This is a hands-on role ideal for someone with strong media instincts, excellent writing skills, and a passion for translating complex medical and technological innovations into compelling narratives. You will work closely with internal stakeholders and external media to help position as the leader in robotic ophthalmic surgery.

Responsibilities:

Support content creation for internal and external channels, including blog posts, LinkedIn, and executive visibility initiatives.
Coordinate social media accounts, ensuring consistent messaging aligned with company strategy.
Draft and edit high-quality written content, including press releases, backgrounders, and briefing documents.
Research and evaluate prospective media channels, conferences, and speaking opportunities and assist in coordinating interviews, press briefings, and events.
Support proactive media outreach and monitor media coverage and industry trends to identify new PR opportunities.

Join our architecture team, the core of silicon development .
Our architects manage all aspects of system chip development and provide specifications to various development teams. In this role you will:
Define the features and specifications of future devices.
Utilize a data-driven approach to model and analyze networks of tomorrow, providing optimal solutions for our customers.
Model, analyze, and present simulation results for cutting-edge networking solutions across various use cases.
Apply strong networking research skills and a robust theoretical background to your work.

We are looking for a dedicated SoC Clocks Design Automation Engineer to join our Networking Silicon team. In this role, youll focus on developing and supporting clock-related design flows and methodologies for SoC and networking chips, ensuring efficient and high-quality design implementation. Youll also chip in to SoC top-level automation and integration activities, building on existing flow infrastructure to improve efficiency and consistency across projects. Introduction

What you'll be doing:

Develop and maintain design automation and methodologies for SoC and networking clock flows.

Collaborate with design, STA, and project teams to ensure timely and high-quality design closure.

Develop and improve SoC top-level automation scripts and flows built upon existing infrastructure and tools.

Support SoC integration and construction flow activities across multiple projects.

Assist in timing, power, and noise analysis to ensure efficient performance.

we are looking for a Junior Physical Design Engineer.
You'll be joining our Physical Design team , which is at the center of the silicon development . Our engineers deal with all chip design aspects: definition, architecture, micro-architecture, design, verification, signoff and validation.
We use the latest silicon technologies and processes to build the largest scale and most complex devices at the edge of feasibility.

we are seeking a Physical Design Engineer.
Meet the Team:
The Physical Design team owns backend methodology and flow development from RTL to GDS. The team plays a critical role in developing high-quality VLSI designs for some of most advanced silicon products.
We work with the latest silicon technologies and processes to build large-scale, complex devices that push the boundaries of feasibility. You will collaborate with experienced engineers across architecture, design, verification, and implementation to deliver high-performance silicon.
Your Impact:
You will be part of the team, which is at the heart of software and ASIC design efforts. As a Physical Design Engineer, you will contribute to backend implementation work across key stages of chip design, helping move complex designs from RTL toward GDS.
You will work on physical synthesis, place and route, optimization, timing closure, and floor planning activities. Success in this role means delivering high-quality implementation results, learning quickly from senior engineers, and helping improve the flow and methodology used by the team.

Leading software test automation and validation strategy and accomplishing objectives through leading the work of direct reports who exercise significant latitude and independence. Oversees automated testing and medical-device software validation across complex Software, cloud, Hardware, edge computers, mobile, AI/ML, and medical-imaging systems to ensure regulatory compliance, requirements traceability, and product quality.


How you will make an impact:

Automation testing Strategy, Standards and Governance
Defines and implements the testing tools, processes, mechanisms, documentation, and automation infrastructure required to deliver software test automation and validation for complex multi-deciplinary products, in accordance with company design procedures, regulatory requirements, and medical-device standards such as IEC 62304.

Automation Team Leadership, Capability and Capacity
Leads, mentors, develops, and manages the automation team and sub-contractors, including task assignment, progress tracking, and professional development. Owns team resources, capacity, priorities, performance expectations, and capability development to ensure the function can meet business and validation needs.

Software Product Testing for Medical-Device
Oversees software-product testing activities and processes across complex Software, cloud, Hardware, mobile, and internally developed SaaS environments, including AI/ML pipelines, 3D processing and visualization, DICOM data workflows, backend services, frontend applications, GPU-based edge-computing systems, mobile applications, and cloud services/APIs.

Cross-Functional Validation Leadership and Senior Stakeholder Influence
Collaborates with R&D, DevOps and QA to design, execute, and maintain tests aligned with software and hardware updates, debugging, and field issues. Ensures traceability between requirements, test cases, and validation results within regulated environments.

Regulated Environment Test Evidence and Compliance Alignment
Maintains validation discipline and test evidence aligned with company design procedures, regulatory requirements, medical-device standards, and traceability expectations in regulated environments. Supports reviews, investigations, and documentation needs relating to validation results, test irregularities, debugging, field issues, regulatory requirements, and medical-device standards.