דרושים » חשמל ואלקטרוניקה » ASIC Physical Design Engineer

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לפני 7 שעות
חברה חסויה
Location: Caesarea
Job Type: Full Time and Hybrid work
we are seeking a Physical Design Engineer.
Meet the Team:
The Physical Design team owns backend methodology and flow development from RTL to GDS. The team plays a critical role in developing high-quality VLSI designs for some of most advanced silicon products.
We work with the latest silicon technologies and processes to build large-scale, complex devices that push the boundaries of feasibility. You will collaborate with experienced engineers across architecture, design, verification, and implementation to deliver high-performance silicon.
Your Impact:
You will be part of the team, which is at the heart of software and ASIC design efforts. As a Physical Design Engineer, you will contribute to backend implementation work across key stages of chip design, helping move complex designs from RTL toward GDS.
You will work on physical synthesis, place and route, optimization, timing closure, and floor planning activities. Success in this role means delivering high-quality implementation results, learning quickly from senior engineers, and helping improve the flow and methodology used by the team.
Requirements:
B.Sc. or M.Sc. in Electrical Engineering or a related field.
2+ years of hands-on experience in VLSI backend design or a relevant physical design domain.
Strong understanding of the Place & Route flow.
Hands-on experience with physical synthesis, place and route, optimization, timing closure, or design floor planning.
Preferred Qualifications:
Understanding of physical construction and integration concepts across backend implementation.
Knowledge of physical design verification methodology, including LVS and DRC.
Familiarity with physical design EDA tools such as Synopsys, Cadence, or similar platforms.
Ability to learn independently, take ownership of assigned tasks, and work effectively with teammates.
Strong problem-solving skills and attention to detail in complex technical environments.
This position is open to all candidates.
 
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לפני 9 שעות
Location: Tel Aviv-Yafo and Caesarea
Job Type: Full Time and Hybrid work
You'll be joining our Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.
You will be leveraging your backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.
Requirements:
A VLSI Design Engineer with extensive experience in backend design
B.Sc./M.Sc. in Electrical Engineering or Computer Engineering with relevant background.
2+ years of hands-on experience in a relevant domain
Strong understanding of Place & Route flow
Preferred Qualifications:
Deep understanding of Physical construction and Integration.
Knowledge of Physical Design Verification methods like LVS/DRC and formal verification.
Experience with PD CAD and Physical Design EDA tools (e.g., Synopsys, Cadence).
Ability to support technology adoption and new tool integration.
Great teammate, self-learner, and able to work independently.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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לפני 9 שעות
חברה חסויה
Location: Tel Aviv-Yafo and Caesarea
Job Type: Full Time and Hybrid work
we are looking for a Physical Design Manager.
You'll be part of the Cisco Silicon One team, which is at the heart of Ciscos software and ASIC design efforts.
As the Physical Design Manager, you will provide strategic and technical leadership to a team of engineers, guiding them through the entire chip design lifecycle. You will be responsible for the group's output, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.
Requirements:
A VLSI Design with extensive experience in backend design
B.Sc./M.Sc. in Electrical Engineering.
Strong understanding of Place & Route flow.
10+ years of hands-on experience in a relevant domain
4+ years of proven Management or Technical Leadership experience.
Preferred Qualifications:
Deep understanding of all aspects of Physical construction and Integration.
Knowledge in Physical Design Verification methodology LVS/DRC.
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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לפני 10 שעות
חברה חסויה
Location: Tel Aviv-Yafo and Caesarea
Job Type: Full Time and Hybrid work
we are looking for a Senior Physical Design Engineer.
Your Impact:
You'll be part of the team, which is at the heart of software and ASIC design efforts.
You'll handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.
Requirements:
A VLSI Design with extensive experience in backend design
B.Sc./M.Sc. in Electrical Engineering.
Strong understanding of Place & Route flow.
7+ years of hands-on experience in a relevant domain
Preferred/Advantageous Qualifications:
Deep understanding of all aspects of Physical construction and Integration.
Knowledge in Physical Design Verification methodology LVS/DRC.
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
Great teammate, self-learning skills, and ability to work autonomously.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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לפני 11 שעות
חברה חסויה
Location: Tel Aviv-Yafo and Caesarea
Job Type: Full Time and Hybrid work
we are looking for a IC Package Design Engineer.
In this role, you will contribute to the development of complex ASIC package designs from early planning and exploration through implementation and tapeout. You will collaborate across package design, layout, SI/PI, and silicon teams to help deliver high‑speed, robust, and manufacturable package solutions.
You will participate in package architecture activities, design tradeoff discussions, and technical problem solving while growing your expertise in advanced packaging technologies and system-level integration. This role provides an opportunity to work on some of the most advanced networking silicon products in the industry within a highly collaborative engineering environment.
Responsibilities:
As a member of the Package Design team, you will:
Lead the package design activities including planning, floorplanning, pinout optimization, stack‑up definition, and high‑speed routing suport.
Collaborate with SI/PI, silicon floorplanning, layout, and manufacturing teams to ensure high‑quality package solutions.
Support package implementation activities and work closely with layout designers to ensure alignment between design intent and physical implementation.
Participate in technical investigations, design reviews, and tradeoff discussions involving performance, manufacturability, and schedule considerations.
Assist in developing and improving package design methodologies, flows, and best practices.
Contribute to debugging, issue resolution, and package bring‑up activities as needed.
Requirements:
Bachelors degree in Electrical Engineering or a related field.
5+ years of experience in package, PCB, or high‑speed design engineering.
Strong understanding of high-speed signal design and power distribution networks (PDN).
Familiarity with industry-standard EDA tools for layout and design.
Strong communication skills with the ability to collaborate and coordinate effectively with cross-functional teams
Preferred Qualifications:
Masters degree in Electrical Engineering
Experience with advanced packaging technologies, interposers, or multi‑die systems
Knowledge of silicon floor planning, signal integrity (SI), and power integrity (PI) considerations
Proven track record to drive design improvements and lead stakeholder coordination throughout the design process
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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לפני 10 שעות
Location: Caesarea
Job Type: Full Time and Hybrid work
we are looking for a ASIC Design Engineering Technical Leader.
Your Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab
Requirements:
B.Sc./M.Sc. in Electrical Engineering from a top university
​Minimum of 8 years of proven experience in a relevant field
RTL design experience
Familiarity with UVM and functional verification methodologies
Preferred Qualifications:
Experience with MATLAB simulations and bit-exact modeling environments
Familiarity with mixed-signal systems and environments
Knowledge and hands-on experience with Clock Domain Crossing (CDC)
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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לפני 10 שעות
חברה חסויה
Location: Tel Aviv-Yafo and Caesarea
Job Type: Full Time and Hybrid work
we are looking for a Logic Design Engineer.
Your Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab
Requirements:
B.Sc./M.Sc. in Electrical Engineering from a top university
6+ years of experience in a relevant field
RTL design experience
Familiarity with UVM and functional verification methodologies
Preferred Qualifications:
Experience with MATLAB simulations and bit-exact modeling environments
Familiarity with mixed-signal systems and environments
Knowledge and hands-on experience with Clock Domain Crossing (CDC)
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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לפני 8 שעות
Location: Tel Aviv-Yafo and Caesarea
Job Type: Full Time and Hybrid work
We are looking for an experienced Design Verification engineer to join our DFT team and help establish and grow DFT DV activity in the Cisco SiliconOne DFT team. This role is relevant for engineers with experience in DV roles, either in DFT DV or in other verification domains, who are interested in becoming familiar with DFT design, verification methodologies, and the challenges of validating testability features in advanced silicon.
Your Impact:
Lead and drive DFT verification activities within the Cisco SiliconOne DFT team.
Develop verification plans, environments, checkers, assertions, and coverage models for DFT features.
Verify DFT architecture and implementation in close collaboration with DFT, design, architecture, and verification teams.
Work on verification of scan, MBIST, IJTAG/JTAG, test access mechanisms, DFT controllers, and related SoC-level test features.
Debug complex pre-silicon issues across RTL, verification environments, and DFT logic.
Contribute to scalable methodologies, reusable verification components, and best practices for DFT DV.
Help bridge between general DV methodologies and DFT-specific design and verification needs.
Requirements:
B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or a related field.
5+ years of experience in design verification roles.
Strong experience with SystemVerilog and UVM-based verification environments.
Experience developing verification plans, coverage models, assertions, and debug flows.
Strong communication skills and ability to work closely with cross-functional teams.
Motivation to learn DFT concepts and become a key contributor in the DFT DV domain.
Preferred Qualifications:
Familiarity with DFT concepts such as scan insertion, memory BIST, ATPG, boundary scan, and silicon test flows.
Experience with complex SoC verification, networking silicon, or high-performance AI-driven silicon.
System-level understanding of large-scale chip architecture and integration.
Ability to build new methodologies and establish verification activity from the ground up.
High attention to detail, ownership mindset, and willingness to grow into new technical domains.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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לפני 7 שעות
חברה חסויה
Location: Tel Aviv-Yafo and Caesarea
Job Type: Full Time and Hybrid work
Join the Front-End Design team, at the core of silicon development. Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.
We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of whats possible.
Your Impact:
Review micro-architecture specifications
Implement Verification environment UVM based
Collaborate with Design engineers to resolve bugs and achieve coverage closure
Work with the firmware/Lab teams to verify chip flows
Perform debug, root-cause analysis, and post-silicon validation in the lab
Requirements:
B.Sc./M.Sc. in Electrical Engineering from a top university
4+ years of experience in the filed
knowledge with UVM and functional verification methodologies
Preferred Qualifications
Experience with MATLAB simulations and bit-exact modeling environments
Familiarity with mixed-signal systems and environments
Knowledge and hands-on experience with Clock Domain Crossing (CDC)
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
לפני 10 שעות
חברה חסויה
Location: Caesarea
Job Type: Full Time and Hybrid work
we are looking for a Senior Asic Design.
Your Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab
Requirements:
B.Sc./M.Sc. in Electrical Engineering from a top university
RTL design experience
Familiarity with UVM and functional verification methodologies
Preferred Qualifications:
Experience with MATLAB simulations and bit-exact modeling environments
Familiarity with mixed-signal systems and environments
Knowledge and hands-on experience with Clock Domain Crossing (CDC)
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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29/07/2026
Location: Caesarea
Job Type: Full Time and Temporary
Required Senior R&D System Application Engineer (12 Months Contract)
Innovation starts from the heart. We put patients first. We invest a significant proportion of our revenue towards research and development to drive and develop groundbreaking medical innovations for structural heart disease. As part of our R&D Engineering team, you will work closely with our Quality and Manufacturing teams to develop the latest tools and technologies to address significant, unmet clinical needs that impact patients lives around the world.
What will you do?
You will be part of an R&D team responsible for the development, integration, and validation of medical device systems. With a strong emphasis on hands-on development, data-driven engineering, with a problem-solving mindset. you will contribute to the full product development lifecycle - from the need, through signal processing and GUI development to system testing and clinical application. This role is designed for engineers who are passionate about building and refining medical device technologies in a multidisciplinary environment.
How youll make an impact:
Develop and improve medical device features within the portfolio as part of a multidisciplinary R&D team that includes mechanical, hardware, and software engineers. Main activities include - procedure development, algorithm development, GUI design and implementation, scripting, test automation, data acquisition, and data analysis and visualization.
Participate in the design and development of system-level features, supporting architecture decisions and translating clinical and functional requirements into working solutions.
Perform hands-on testing of medical device systems (implant systems, hardware, and software), including functional, integration, and exploratory testing to validate design performance and clinical readiness.
Lead test design efforts, including writing test cases, test procedures, and test reports. Collect, analyse, and summarize test data to support design decisions and issue investigations.
Execute and support test protocols in lab and simulated clinical environments. Accurately document results, observations, and issues to ensure traceability and compliance.
Collaborate with stakeholders and colleagues - including caregivers, R&D engineers, clinical specialists, marketing, and quality teams - to understand system behaviour, clinical workflows, and end-user needs, ensuring that developed solutions align with real-world application requirements.
Requirements:
What you'll need (Required):
Degree in an engineering discipline. Biomedical, Electrical, Software or Computer Science, Math, Information Systems, or a related area preferred.
Bachelor's degree + minimum of 3 years of experience in R&D roles.
Familiarity with medical devices, clinical systems, and product development processes.
Advantage - programming experience (Python, C++, LabVIEW, similar); experience with GUI development frameworks and algorithm design is a plus.
Solid technical aptitude with the ability to understand system-level designs, software development lifecycle, and associated challenges and risks; ability to work closely with engineers across disciplines.
What Else we look for (Advantage):
Strong analytical thinking and problem-solving skills with a development-oriented mindset.
Experience or strong interest in algorithm development, data processing, and GUI-based application development.
Ability to work collaboratively in cross-functional R&D teams and contribute across the development lifecycle - from concept through verification.
Hands-on, detail-oriented approach with a strong willingness to learn and adapt.
Ability to follow procedures accurately and document work clearly.
Comfortable working in lab environments and handling biological materials and technical equipment.
Clear written and verbal communication skills in English.
This position is open to all candidates.
 
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