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As a member of our Physical Design group, you will take an integral part in bringing large scale SoCs to life, helping us deliver the next generation of our ground-breaking products.
You will own the physical design cycle at the partition/IP/Chip levels, including netlist to GDS implementation and verification.
Are you ready to join some of the world's leading engineers and work with state of the art design flows and process technology?
If you possess the knowledge and experience in any of the physical design domains and practices with track record of tape-outs in sub-micron technology, come join our group!

As a member of our Physical Design team in this highly visible role, you will directly own implementation and verification of design partition(s) / IPs (netlist to delivery of our final GDS) for a highly complex SoC utilizing state of the art process technology.
* Implementation - Block level PnR, floor-planning, clock, power planning and distribution.
* Verification and Analysis - Static Timing closure using commercial tools, Physical Verification as well as Electrical/Power Analysis (EM / IR-Drop / Xtalk / noise )

This role is for a analog IP lead who will enable us to produce fully functional first silicon IP designs. The responsibilities include all phases of silicon development from definition to high quality production.


Specifying requirements and circuit architecture for analog blocks and sub-blocks of an IP, lab bring-up, characterization and debug, write specifications, test plans and characterization reports, work with chip design teams, system HW and SW design teams, ATE PE.

You will be responsible for:
Develop the circuit design of the IPs analog blocks following established design guidelines based on microarchitecture spec. Own all aspects of circuit design development.
Work and collaborate with other designers in the group to deliver results.
Work with FE & BE teams to ensure quality analog integration.
Work with power/performance and functional verification team to define and validate operation sequences.
Work with multi-disciplinary teams to make sure designs are delivered on time and with highest quality by incorporating proper checks at every stage of the design process.
Work with post silicon validation groups to ensure the design meets the power/performance targets.

we bring connectivity and intelligence to everyday products and packaging; things previously disconnected from the internet of things. our platform combines cloud services and iot pixels, computing elements that can power themselves by harvesting radiofrequency energy. this revolutionary mixture of cloud and semiconductor technology is used by some of the worlds largest brands, food, and pharmaceutical companies to change how we make, distribute, sell, use, and recycle products. our investors include amazon, verizon, ntt docomo, qualcomm, pepsico, and softbank vision fund 2. join us and help pave the way for the new iot.
our TEST & product team is responsible for keeping a target of a very aggressive cost limit of the production testing (wafer sort) while performing comprehensive testing of all the units functionalities. this involves:
development of the tests using the teradyne uf tester.
development of unique and advanced TEST hw.
monitoring and analyses the production data.
fa (failure analysis) when issues are discovered.
innovative dft (design for testability) with the design team.
responsibilities:
development of wafer sort TEST programs through a close relationship with the system team.
development of the future products dft and dfm through close collaboration with the design team.
improvement of the production data analysis and reports through close relationships with the cloud and data teams.
working with the external abroad TEST houses.
decision-making based on massive data analysis (pass criteria, improvements of the tests, identification of failures).
integrate new and innovative testing methods for a new technology sector.
specify and work with external vendors for the tester hw (probe-card and load-board).
specify and work with external vendors for the htol hw, TEST program.