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We are seeking a Front-End Integration Engineer for the NIC Silicon group. Join our team in our Networking business unit and be part of the innovative build and implementation of the next generation Network Adapter Silicon chips. Contribute to the development of powerful communication devices.

What You'll Be Doing:

Own and maintain Continuous Integration pipelines. Monitor, complete, and fix daily and nightly CI flows in front-end build areas. These include Lint, Synthesis, Equivalence Checking and Simulation.

Automate EDA Flows: Build, develop, and maintain robust automation scripts using Python, Tcl scripting, and Shell to integrate EDA tools (Synopsys, Cadence) into automated build pipelines.

Manage Perforce Integration: Maintain multi-IP branch/stream strategies, manage workspace specs, complete hardware build drops, and handle release labels/tags in Perforce (Helix Core).

Support Engineering Teams: Act as the primary point of contact for RTL and verification engineers to debug flow crashes, bottlenecks, environment setups, and CI failure reports.

Enforce Quality Gates: Implement automated check-in and change list triggers to run sanity checks, linting, and style enforcement before code is committed to main streams.

Optimize Infrastructure: Monitor compute farm resources (LSF) and storage usage to reduce pipeline runtime and improve overall execution efficiency.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Staff / Principal ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects.
As a Staff / Principal ASIC Design Engineer, you won't just build chips-you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Design Ownership & Implementation
Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support
Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions
Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams
Quality Assurance & Design Optimization
Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient
Apply design techniques to meet PPA (Power, Performance, Area) targets
Contribute to design quality through verification and validation activities
Methodology Innovation & Collaboration
Participate in design methodology improvements and tool automation initiatives
Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter
Collaborate effectively across teams to ensure seamless integration.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Chip Top Physical Design Engineer focusing on implementation to join our local engineering powerhouse from the ground up.
If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us.
As a Physical Design Engineer, you will be a key hands-on member of our PD Team in the Israel R&D center. You will execute the physical design of the SoC Top level for chips that drive the worlds largest AI clusters. You will be deeply involved in all PD disciplines of the chip, driving the tape-out (T.O.) GDS to meet strict signoff criteria (Timing, LVS, EMIR, DRC, PV, etc.), ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.
Key Responsibilities
Execute SoC Top-level physical design and actively drive full-chip convergence
Perform Top-Level physical implementation, including floor-planning, Place & Route (P&R), Clock Tree Synthesis (CTS), Power/Clock distribution, Power Integrity, and Timing/Physical signoff
Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power, Performance, and Area (PPA). This involves participating in feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)
Resolve complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon
Collaborate closely with the Package team on Bump-map-to-Ballout design, taking all signal integrity aspects into consideration.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Staff/ Principal Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly.
As a Staff/ Principal Design Verification Engineer, you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world's largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Verification Environment Development
Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks
Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing
Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified
Coverage & Quality Assurance
Implement functional coverage models and analyze results to identify gaps in the verification process
Drive designs toward 100% verification closure through comprehensive test development
Contribute to verification methodology improvements and best practices
Debug & Cross-Functional Collaboration
Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle
Apply analytical skills and debugging techniques to solve intricate verification challenges
Collaborate effectively in a fast-paced, team-oriented R&D environment.

Were looking for a highly skilled Technical Support Engineer to lead the charge in troubleshooting complex technical issues, ensuring exceptional customer satisfaction, and providing strategic solutions. Youll play a key role in documenting solutions, escalating critical cases, and leveraging your cloud expertise to deliver unparalleled support and build strong, lasting relationships with our customers.
Responsibilities:
Provide accurate and timely support via Slack, chat, or email to troubleshoot and resolve customer issues.
Diagnose and resolve technical problems, escalating complex issues to R&D or Product when needed.
Build strong relationships, educate customers on product features, and maintain a professional, supportive tone.
Create and update support documentation while logging all interactions in the support system.
Enhance skills through ongoing training to maintain technical excellence and deliver top-tier support.

Our HW team designs innovative end-to-end connectivity solutions for GPU servers. Our products optimize data center performance and deliver industry-leading bandwidth and scalability. Our products are focused on delivering the most optimized power - performance communication solutions for industries like AI, ML, Cloud, Media and Entertainment as well as any other industry that can benefit from our Datastream acceleration.



What you'll be doing:

Lead Pioneering Switch System design from concept to mass production.

Collaborate and integrate with all HW project fields: Board Design, Mechanics, Thermal, PCB Layout, Production, Software/Firmware, RTL and more.

Project decision maker - Technical focal point.

The position consists of product specification definitions, electrical schematics, component selection, layout guidance, hands-on testing in a lab environment, accompanying production and qualification processes.

We're seeking a talented, versatile, and highly independent Full Stack Engineer to join our engineering team. You will be in charge of end-to-end development and significantly impact both the product and technical decisions.

Responsibilities
Lead development processes from ideation to production
Develop, maintain, and imperialize the products application layer (front end & back end)
Collaborate with product, medical, and software teams across the organization
Build a customer-centric product with a deep understanding of the complex healthcare industry

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, We are looking for a Physical Design CAD Engineer with at least 3 years of hands-on experience in digital implementation flows. The ideal candidate is highly technical, curious, and eager to drive innovation by combining strong physical design knowledge with modern automation and GenAI-based methodologies.
This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the parasitic extraction (PEX) methodologies and flows for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the accuracy and efficiency of our extraction environment, ensuring that our high-speed designs are modeled with the highest precision from RTL to GDSII.
Key Responsibilities
The Engineer will develop, maintain, and improve CAD flows and methodologies for physical design teams, supporting advanced implementation stages from synthesis through place and route, timing closure, power optimization, and signoff readiness.
Key responsibilities include:
Develop and support physical design CAD flows using industry-standard EDA tools
Build automation infrastructure for implementation, analysis, reporting, and debug
Support design teams in areas such as synthesis, floorplanning, placement, CTS, routing, timing, power, and physical verification
Create scripts and utilities to improve productivity, quality of results, and flow robustness
Support and enhance flows based on Synopsys Fusion Compiler
Explore and integrate GenAI solutions to accelerate debug, automate repetitive tasks, improve reporting, and enhance engineering productivity
Analyze tool results, logs, QoR metrics, timing reports, congestion, utilization, power, and design-rule issues.

We are seeking a Senior Software Architect to lead and shape the architectural vision of our SaaS healthcare platform, guide the adoption of cutting-edge AI technologies, and ensure our solutions remain scalable, secure, and future-ready. This is a hands-on, strategic leadership role that combines visionary system design, proof-of-concept development, and AI-first innovation enablement.

Responsibilities
1. Architectural Leadership

Define, communicate, and evolve the platforms architectural vision to ensure alignment with business goals.
Lead high-level design discussions and decisions for new and existing products.
Establish and maintain architectural principles, standards, and patterns across all engineering teams to ensure consistency and coherence.
Drive cloud-native architecture in AWS with a strong focus on scalability, availability, performance, and cost efficiency.
2. Innovation & Emerging Technology

Build POCs and pilots for new solutions, frameworks, and AI capabilities.
Evaluate emerging trends in AI, LLMs, MCPs, agents, and developer productivity tools, ensuring strategic adoption where relevant.
Initiate projects/features to solve widespread problems (including work with Support, DevOps, Infosec)
3. AI Tooling Evangelism

Spearhead engineering-wide adoption of AI-assisted development workflows, including developer productivity tools, code copilots, automated quality checks, and automated documentation.
Define best practices, guidelines, and governance for AI usage in development (e.g., Cursor configuration rules, prompt engineering standards).
Educate and mentor teams on effective AI utilization for engineering, product, and operational tasks, taking into account security, costs, and compliance.
4. Technical Governance & Best Practices

Overall ownership of the system scalability, COGS, and stability of the product(s)
Define standards for coding, testing, CI/CD, and monitoring.
Enforce architectural and design reviews for key initiatives.
5. Cross-functional Collaboration

Work closely with Engineering, Product, Data Science, DevOps, and Security teams to deliver well-architected solutions.
Communicate complex technical concepts to non-technical audiences, including executives and external partners.

We're looking for a motivated student who wants to take their first step into the high-tech world - and not just anywhere, but at one of the fastest-growing cybersecurity companies out there, working on some of the most interesting challenges in the industry. This is an entry-level position with real room to grow: you'll get hands-on training, mentorship, and the chance to develop into a full Technical Support Engineer role over time.
Responsibilities:
Provide accurate and timely support via Slack, chat, or email to help troubleshoot and resolve customer issues.
Learn to diagnose technical problems and escalate complex issues to R&D or Product when needed.
Build strong relationships with customers and maintain a professional, supportive tone.
Help create and update support documentation, and log interactions in the support system.
Continuously build your technical skills through ongoing training and mentorship.

we are looking for a Technical Support Engineer
Responsibilities
Resolve customer issues daily, ensuring timely responses and high levels of customer satisfaction
Proactively manage the day-to-day resolution of customer issues in a timely (SLA) manner and maintain their high satisfaction
Contribute to methodologies, best practices, and techniques to improve our support process
Build and contribute to Navinas technical support knowledge base.
Work closely with R&D, Product, Customer Success, and our Medical team for complex problem-solving and time-sensitive escalations.