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Which department will you join?
our companys Unit Level Verification Team in Haifa is looking for an experienced verification engineer to be involved in the development of
our companys future AI and deep learning HW accelerators.
This is an exciting opportunity to join a team of highly talented engineers, working on the most cutting-edge technologies to deliver
our companys EyeQ future chips, aimed to power the worlds first fully Autonomous Vehicle!
What will your job look like?
Define, implement and enhance verification environments using UVM methodology.
Write and debug tests that combine UVM methodology and SW code.
Identify and write various types of coverage measures.
Collaborate with designers, architects, and SW developers from Haifa and Jerusalem teams to deliver the most comprehensive verification environment.
Integrate Industry Standard (such as AXI and OCP) and other 3rd party VIPs.

our company's EyeQ Platform Group (EPG) is seeking a motivated Formal Verification Engineer to join our team and contribute to development of hardware verification environments.
This position offers an opportunity to apply formal methods to verify the correctness of various complex digital systems.
This is an exciting opportunity to join a team of talented engineers, working cutting edge technologies in the field of autonomous vehicle.
What will your job look like:
Be the owner of formal verification environment from first draft to sign-off stage
Apply formal methods to verify the correctness of various complex digital systems
Work with HW architects\designers to define assumptions, rules and cover properties
Help define the formal verification methodology and environment to be applied by the team
Explore new Formal methods and Tools
Work with tools like Cadence JasperGold, Verisium manager, Xcelium, Indago
Analyze verification results, identify bugs, and collaborate with engineers to resolve design issues
Develop generic formal blocks\functions of commonly used logic, to be later used off the shelf.

We are looking for an experienced Hardware Team Lead to manage our Board Design Engineering team within the AV department. In this critical role, you will drive the development of cutting-edge automotive products by owning the design and delivery of high-performance electronic boards and systems. Your leadership will ensure projects meet the highest standards of quality, performance, and innovation.
What will your job look like?
Lead and Do: Combine strong technical leadership with hands-on hardware engineeringthis role is both strategic and actively involved in execution.
Team Management: Mentor, guide, and grow a high-performing team of hardware engineers, while setting clear technical direction and expectations.
End-to-End Project Ownership: Drive the entire hardware development lifecyclefrom architecture and schematic design to validation and release to mass production.
Design Leadership: Personally contribute and oversee electrical design, schematic reviews, component selection, and layout best practices.
Lab Engagement: Stay closely involved in board bring-up, debugging, and validationworking side by side with engineers to solve tough technical challenges.
Cross-Team Collaboration: Act as a key point of contact across software, mechanical, architecture, and manufacturing teams to ensure seamless product integration.
Customer-Facing Leadership: Represent the hardware team in technical discussions with customers, demonstrating both leadership and in-depth technical knowledge.

'קwe are looking for a Emulation Engineer to join the Radar VLSI team and drive the development of the next generation ASIC Sensors.
What will your job look like:
This role is all about making high-end Emulation environment base on new designs.
Building and integrating complex components, working with cross-functional engineering teams, and making systems that will change the way we drive.
This role requires an engineer who loves challenges and knows how to bring engineering excellence while considering complicated constraints.
You will work with members of a cross-functional talented,
You will lead the Emulation development for the VLSI team.
You will work closely with SW Engineers, Logic Engineers, Verification Engineers, and others.
You will serve as an expert matter for your domain, which has the full responsibility to drive & implement improvements and new ideas.

we are the world leader in automotive and driving assistance systems, developing the world's most advanced software technologies and hardware architectures.
Were looking for a strong expert to take part in a revolutionary large-scale project to transition our companys cutting-edge SW stack into the Bazel build system.
What will your job look like:
Designing, managing, and developing the build system infrastructure for our unique large-scale software stack, including DL training and deployment projects, real-time embedded software, and open-source projects.
Working closely with the DevOps team to ensure that the build system infrastructure is secure, reliable, and easily scalable.
Optimizing build times using cutting-edge distributed systems and caching technologies.
Troubleshooting build issues and provide guidance on best practices for build system management.
Building a strong echo system and infrastructure on the server side to ensure proper monitoring and debugging.
Keep up to date with the latest developments in the Bazel build system and suggest improvements to the existing build infrastructure.
Working closely with the development team to learn the technologies and provide guidance on best practices for build system management, ensuring that all software builds are reliable, efficient, and scalable.

We are our company's Production Test team - responsible for the definition, development, and deployment of production test operations for the worlds most advanced SoCs for ADAS and self-driving vehicles.
This is your opportunity to join a team during its initial forming stage and leave your mark as our company assumes full ownership for its silicon production operations to enable high volume manufacturing for cutting-edge automotive products.
What will your job look like:
Setup and maintenance of test, diagnosis, and yield analysis infrastructure using the Exensio data analytics platform.
Enable end-to-end production traceability and effective yield monitoring and quality control across all stages of production.
Implement advanced flows for outlier detection, escape prevention and adaptive tests to maximize product quality. Interact with OSATs to define checkpoints for key quality metrics.
Collaborate with Test Engineering (TE) teams to ensure test quality and recommend test limits for production lots and corner lots based on system specifications, yield, and Cpk targets.
Drive yield improvement and test-time reduction activities based on Wafer Sort (WS), Final Test (FT) and System Level Test (SLT) production data.
Analyze foundry Wafer Acceptance Test (WAT) data from development, corner lots, and qualification lots. Collaborate with wafer foundry to correlate WAT with WS test data to identify and resolve systematic yield issues.
Drive volume ramp and mass production through volume data analytics. Manage yield excursions and material disposition in a timely manner.

our company EyeC VLSI team - a group designing the chips for RADAR systems for ADAS and autonomous cars.
Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an end to end responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges
Were looking for a Physical Design STA Technical Expert to join the growing Physical Design Team, responsible for state of the art SoC design from definition to Tape-Out.
What will your job look like:
Leading FC timing activities & methodologies for brand New SoC, from definition to TO.
Writing design constraints (SDC) for FC/IP/Block levels for all modes.
Involved in chip architecture definition for functional & DFT domains.
Working in close collaboration with the front-end & architecture team.
Working with engineers to identify and overcome roadblocks and obstacles.
Defining AC timing from spec to implementation.
Supporting complex clock structures.

our company EyeC VLSI team - a group designing the chips for RADAR systems for ADAS and autonomous cars.
Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an end to end responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges
Were looking for a Physical Design Expert to join the growing Physical Design Team, responsible for developing our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS with horizontal ownership.
Floorplan exploration and collaboration with front-end and architecture teams.
Synthesis exploration and final synthesis including: SDC definition, Scan insertion, Lint, LEC, UPF-LP & Spyglass verification.
Place & Route: from Synthesis to final layout and signoff verification on all tools and floors, with target to achieve best PPA.
STA: timing analysis, working with Sub System and Full Chip owners to manage block and top level constraints for synthesis, P&R and signoff.
Signoff : on all physical design domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.

You will join a team of talented and experienced Signal/Power Integrity (SI/PI) & Electrical Validation engineers with wide scope of responsibility, from Pre-Silicon SI/PI simulations to Post-Silicon Electrical validation and debugging, covering all High-Speed interfaces and Power Delivery of our company EyeQ ASIC products.
What will your job look like:
You will deal with design, simulations, optimization and debugging of high-speed interfaces - like LPDDR4/5, PCIe Gen4/5, C/DPHY, Multi Giga-Bit Ethernet, High-Speed interfaces over Power Cables, Power Delivery Networks.
You will develop Layout guidelines, review the physical design process and check its quality.
You will deal with state-of-the-art signal & power integrity simulation tools and methodologies, advanced results analysis, optimization/verification of our company and customers' PCB designs, etc.
This is a dynamic work environment that requires interfacing with Silicon & Hardware design engineers, IP providers, Electrical and System Validation teams, Customer Application Engineers, EDA tools vendors, and product managers.
The proximity to Electrical Validation activities - we are a single SI/EV team - is another strong advantage, enabling joint simulation-measurements efforts.

we are a global leader in autonomous driving technologies and advanced driver-assistance systems (ADAS). Our cutting-edge solutions, including the EyeQ chip, company SuperVision, company Drive, and company Chauffeur, leverage computer vision and machine learning to enhance vehicle safety and enable self-driving capabilities. Integrated into millions of vehicles worldwide, our technology is redefining the automotive industry and driving the evolution towards smarter, safer, and more autonomous mobility.
In our group, we research, develop, and deploy state-of-the-art lidar based techniques to achieve world-class results, enabling the safe development of Autonomous Driving features and Advanced Driver Assistance Systems.
What will your job look like:
Research, design, develop, and implement lidar based algorithms in both Python and C++ for solving complex problems
Evaluate existing models and techniques, and propose innovative approaches to improve algorithm performance and accuracy
Examine your algorithms on large-scale real-world data from our data collection vehicles across the globe
Collaborate with cross-functional teams to understand requirements and develop solutions
Optimize existing algorithms to improve performance and scalability.

we are looking for an Embedded SW Engineer for SystemC Modeling that include Performance and Program view Modeling. You will be part of VLSI emulation team , working on current and next-generation designs for next generation sensors.
The SystemC models are fundamental parts of the VLSI chip infrastructure, they are used during HW architecture definition phase and by SW developers for system shift left.
What will your job look like:
You will work on Critical performance analysis and optimizations on the ASIC micro architecture as multi-NOC , DDR and CPU .
You will work on developing SystemC models that describe the RTL models on High level language and enable true system . level shift left for the embedded SW team.
You will have the opportunity to work on state-of-the-art simulation and profiling tools and adopt them to our company's needs.
You will work closely with HW architects and SW/Algorithms developers.