דרושים » ניהול ביניים » Embedded Linux OS Architect

we are an agile defense-tech startup tackling the most complex challenges in counter-drone and unscrewed defense. With hundreds of combat-proven systems deployed by the IDF and global partners, we are now engineering the next generation of C-UxS (Counter-Uncrewed Systems). We leverage advanced electronic warfare and kinetic measures to detect and neutralize hostile threats. If you want to push technological boundaries while safeguarding Israel and our allies, join us at this pivotal stage of our growth.
This is a unique opportunity to join a company at a pivotal growth stage and help shape its products, culture, and future.
We are seeking an experienced Senior Real-Time Embedded Software Engineer to join our core engineering team and develop advanced software for high-performance, mission-critical embedded systems.
Key Responsibilities
Own tasks, infrastructure, and subsystems end-to-end, from requirements analysis and system modeling through design, implementation, testing, integration, and deployment.
Design, implement, integrate, and optimize real-time software for MCU-based platforms.
Translate system-level requirements into robust and efficient software solutions.
Lead software integration and validation on target platforms, including troubleshooting and system bring-up.
Contribute to the development and improvement of software infrastructure and platform-level capabilities.
Work closely with Hardware, Algorithms, and System Engineering teams within a multidisciplinary R&D environment.
Collaborate with relevant stakeholders to drive tasks and projects forward efficiently.

Required Staff Embedded Firmware Engineer, High Speed DSP
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a Staff Embedded Firmware Engineer for High-Speed DSP, you will architect and define the low-level firmware and control loops powering the world's most advanced physical-layer communications silicon. Sitting at the critical intersection of digital signal processing (DSP), hardware-software co-design, and real-time systems, you will lead the development of adaptive algorithms, error correction (FEC), and link-telemetry frameworks. Your work will directly bridge the gap between high-performance hardware pipelines and our planetary-scale AI infrastructure, transforming complex communication systems theory into reliable, real-time silicon execution.
Responsibilities
Define the long-term firmware roadmap and hardware-software partitioning for physical-layer interfaces, determining the optimal balance between hardware-fixed logic and programmable firmwarm.
Architect advanced "in-situ" monitoring systems and firmware-driven diagnostics to track physical-layer link health, Bit Error Rate (BER) trends, and channel quality across millions of ports in real-time.
Design, model, and implement bare-metal or RTOS firmware to control high-speed transceivers, managing real-time adaptive loops, clock and data recovery (CDR), and physical-layer calibration.
Partner with TPU Systems, Networking Software, and High-Performance Computing (HPC) teams to ensure silicon firmware integrates seamlessly with global cluster management and collective communication frameworks.
Identify and de-risk hardware-software interface bottlenecks (e.g., register maps, driver latencies, and boot-up sequencing) that impact our AI infrastructure.

We are looking for an architect to work on the invention and development of new SW visible CPU technologies to improve performance of SW scenarios related to memory ordering, memory coherency, multithreading, synchronization, memory safety, caching, etc.
The minimal tasks of this role are:
1. Modeling of new memory related architectural features in the existing CPU performance simulator
2. Development of performance tests or adaptation of existing workloads to be suitable for simulation
3. Conducting performance studies for the workloads of choice either in the performance simulator or on a real chip
4. Develop analysis, conclusions and recommendations based on the above activities
The role can comprehend much more than that depending on the skills, talent and experience of the candidate creating a career path over time. For example, to invent new instructions and mechanisms to overcome significant performance bottlenecks in these areas, refinement and further development of ideas provided by others. Possible participation in development in additional domains
If you want to be part of something bigger, if you are a team player with excellent communication skills and motivation to revolutionize data-center technology, youre welcome on board!

Looking for a CPU performance modeling architect to take responsibility over the performance aspects of new CPU instructions or modes of operation. The role includes but is not limited to:
Partners with lead SW and HW architects to co-invent optimal HW and SW solutions that come to address requirements. Influences the direction based on experiments and simulation data.
Models CPU functionality, performance and/or power in pre-silicon simulators
Defines and runs performance experiments to aid feature definition. Such experiments can be performed on a pre-silicon simulation environment or in a real system or on a combination of both or even in combination with analytical models.
Provides experimental/proof of concept for new features and implementation alternatives meeting performance constraints.
Analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usages.
Potentially (in the future), lead a team doing above activities.
An adequately qualified candidate can also become the leader of definition for some features in addition to all the roles above.

The CPU Architect will take charge in defining a processor core that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.