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we're the driving team behind groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
perform rtl development (e.g., coding and debug in verilog, systemverilog, vhsic hardware description language (vhdl)), function/performance simulation debug, and lint/cdc/fv/upf checks.
participate in synthesis, timing/power, and fpga/silicon bring-up.
participate in TEST plan and coverage analysis of the block and SOC -level verification.
communicate and work with multi-disciplined and multi-site teams.

be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.as a power and signal integrity engineer, you will be responsible for the design and characterization of signal and power integrity of our ic designs. you will design the external electrical interfaces of the device, from their signal/power-integrity and electrical usage perspectives and set up methodologies, perform simulations, silicon characterization and correlations to ensure our ic designs meet systems design budgets and achieve the highest performance. you will work with systems architects, asic design, systems engineers, and partner cross-functionally with teams and external vendors/partners.the ml, systems, and cloud ai (msca) organization at our designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all our services (search, youtube, etc.) and our cloud. our end users are cloud customers and the billions of people who use our services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including our clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
generate precise electrical models (e.g., s-parameters, spice models) for components such as packages, pcbs, and connectors for use in simulations.
simulate high speed interface electrical behavior using hspice or other circuit simulators.
execute lab measurements utilizing TEST equipment like oscilloscopes, vector network analyzers (vna), time domain reflectometers (tdr), spectrum analyzers to validate simulation outcomes and debug signal and power-related issues on silicon prototypes and boards.
establish design rules and guidelines for optimal signal/power integrity during pcb and package layout, ensuring high production yield and reliability.
document design specifications, analysis results, and validation reports to ensure compliance with standards and for future reference, while collaborating extensively with cross-functional teams, including asic architects, digital/analog designers, physical design/layout engineers, and system engineers

in this role, you will help build socs by driving quality and reliability processes from the integrated circuit (ic) perspective. working with various cross-functional teams, you will develop quality and reliability specifications, develop and deploy design guidelines, and develop and execute TEST plans. within the larger organization, you will collaborate with global hardware quality and reliability, silicon design, validation, and engineering teams. you will have an understanding of ic flows, wafer processing, testing, qualification, yield, reliability, and failure analysis.the ml, systems, & cloud ai (msca) organization at google designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all google services (search, youtube, etc.) and google cloud. our end users are googlers, cloud customers and the billions of people who use google services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including google clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
define and lead qualification hardware and TEST developments in front of internal teams and external vendors.
define and execute silicon and package qualification activities (e.g., htol, elfr, esd/lu, b/hast, thb, etc.).
extract, manipulate, and analyze large volumes of data from silicon and package qualification programs (e.g., htol, elfr, esd, lu, uhast, tct, etc.), high volume mfg, and field returns to identify failure mechanisms, reliability trends, and opportunities for yield, quality, and reliability improvement.
own cross-functional investigation of ic quality and reliability issues to identify root causes and develop solutions (e.g., rma triage, analytics, failure analysis, etc.).
develop and implement physics-based statistical quality and reliability models (e.g., elf, tddb, nbti, hci, time zero failures, etc.) to predict silicon device failure mechanisms, degradation patterns, and lifetime behaviors.

about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next-generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.the ml, systems, & cloud ai (msca) organization at google designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all google services (search, youtube, etc.) and google cloud. our end users are googlers, cloud customers and the billions of people who use google services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including google clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
lead the schematic capture and component selection for high-density, multi-layer pcbs (20+ layers) incorporating high-power asics (tpus/cpus), fpgas, and high-speed memory (hbm/ddr5).
design and validate high-speed interfaces including pcie gen 6.0/7.0, 400g/800g/1.6t ethernet (pam4). collaborate with signal integrity (si) engineers to define routing constraints and stack-up.
design multi-phase power regulators (vrms) capable of delivering >1000a currents with fast transient response for ai processors.
work with pcb layout designers to guide placement and routing of critical signals and power planes.
lead the lab bring-up of first-silicon/first-board by debugging hardware issues using oscilloscopes, tdrs, and logic analyzers to root-cause failures to component, assembly, or design issues.

about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
as part of our server chip design team, you will use the asic design experience to be part of a team that creates the SOC vlsi design cycle from start to finish. you will collaborate with design and Verification engineers in active projects, creating architecture definitions with rtl coding, and running block level simulations.the ml, systems, & cloud ai (msca) organization  designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all google services (search, youtube, etc.) and google cloud. our end users are googlers, cloud customers and the billions of people who use google services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including google clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
lead the design activities at ips, subsystems(s.s) and SOC.
plan, execute, track progress, assure quality, report status of the assigned activity.
lead a team of designers both directly and in teams.
define the block/ SOC level design documents such as micro architectural specifications.
own ip, s, SOC strategies for clocks, resets, and debugs. enforce global methodologies and drive enhancements.

in this role, you will be a key player in identifying and attracting talents to google cloud in israel. you will directly support the growth and success of ai and infrastructure business in israel, enabling the silicon engineering team to continue leading innovation in its respective product areas. you will be responsible for engaging and hiring candidates for a variety of silicon engineering roles, including design, design verification, physical design, silicon validation, silicon engineering and operations, and additional sub-domains. you will collaborate with hiring managers to understand the specific needs of each role and develop targeted hiring strategies to deliver for the business.great just isn't good enough for our people operations team (known elsewhere as "human resources"). we bring the world's most innovative people to google and provide the programs that help them thrive. whether recruiting the next googler, refining our core programs, developing talent, or simply looking for ways to inject some more fun into the lives of our googlers, we bring a data -driven approach that is reinventing the human resources field.
responsibilities
conduct candidate assessment for potential roles and identify team alignment based on understanding of the organization/function and role profiles.
evaluate candidate skills and client needs, screening them for interviews and managing the interview process with some guidance.
collaborate with key business leaders, recruiting, and hiring stakeholders to build solutions to defined objectives.
manage headcount for cross-project client groups to support accurate tracking and influence headcount allocation, ensuring accurate mapping of job postings to open headcount, identifying trends/insights to shape hiring strategy and priorities, assisting clients with prioritization of requisitions, reconciliation of headcount, and optimum distribution with some guidance.
develop and execute cross-project targeted recruiting initiatives to meet established goals and objectives, influence hiring managers on their hiring strategy.

Role Overview We are seeking a proactive, high-energy Executive Assistant to support our CEO. This role is designed for a "force multiplier", someone who can anticipate needs before they arise and seamlessly navigate the fast-paced environment of a growing startup. The PA is expected to present a "find a way" attitude; you will be expected not only to present the problem but also bring potential solutions. We value work-life harmony and respect your time, but we move fast and we need a partner who can keep pace, while this is not a shift-based 24/7 role, it requires a high degree of responsiveness and the willingness to be available for urgent, time-sensitive matters outside of standard business hours. Core Responsibilities: Proactive Scheduling: Manage a complex, high-volume intense calendar. Youll be responsible for "auditing" the CEOs time to ensure it is utilized for top-tier priorities. Travel & Logistics: End-to-end management of domestic and international travel (Flights, hotels & car rental), including detailed itineraries, "Plan B" travel contingencies, and local transit. High Responsiveness: Act as the primary point of contact during "crunch times." You are comfortable being the first call for the CEO when a flight is canceled at midnight or a meeting is moved. Communication Flow: Draft correspondence, manage high-volume email inboxes, and ensure the CEO is briefed on all internal and external communications. Prioritization: Plan and allocate CEOs time based on priorities between customers, investors, employees, partners, suppliers, media and others.

As an ML Software Engineer with a focus on low-level and CUDA-based optimizations, you will play a key role in shaping the design, performance, and scalability of machine learning inference systems. Youll work on deeply technical challenges at the intersection of GPU acceleration, systems architecture, and ML deployment.
Your expertise in CUDA, C/C++, and performance tuning will be crucial in enhancing runtime efficiency across heterogeneous computing environments. Youll collaborate with designers, researchers, and backend engineers to build production-grade ML pipelines that are optimized for latency, throughput, and memory use, contributing directly to the infrastructure powering next-generation AI products.This role is ideal for an engineer with strong systems-level thinking, deep familiarity with GPU internals, and a passion for pushing the boundaries of performance and efficiency in machine learning infrastructure.

Responsibilities
Design and implement highly optimized GPU-accelerated ML inference systems using CUDA and low-level parallelism techniques
Optimize memory, compute, and data flow to meet real-time or high-throughput constraints
Improve the performance, reliability, and observability of our inference backend across diverse compute targets (CPU/GPU)
Collaborate with cross-functional teams (including researchers, developers, and designers) to deliver efficient and scalable inference solutions
Contribute to ComfyUI and internal infrastructure to improve the usability and performance of model execution flows
Investigate performance bottlenecks at all levels of the stack-from Python to kernel-level execution
Navigate and enhance a large, complex, production-grade codebase
Drive innovation in low-level system design to support future ML workloads

As a Research Scientist in Model Evaluation, you are the ultimate authority on model quality and utility. You will design the automated judges, reward models, evaluation datasets, and benchmarking ecosystems that determine the future of LTX. Your mission is to provide the "ground truth" for our pre-training and post-training teams. You will blend the rigor of a researcher with the intuition of a product-thinker, developing metrics that capture both the aesthetic soul of a video and the functional precision required for high-stakes professional use.

Key Responsibilities
Steer Training & Research: Systematically evaluate model checkpoints to provide actionable insights that guide training experiments and architectural decisions.
Design Benchmark Ecosystems: Develop and run rigorous benchmarks for release candidates against competitive models, ensuring LTX-2 remains world-class.
Build Next-Gen Metrics: Develop robust automatic metrics and Reward Models (e.g., for RL, ITS, auto-research agents) that quantify complex attributes like temporal coherence, physical correctness, spatial accuracy, and foley synchronization.
Diagnose & Analyze: Perform deep root-cause analysis on model failures, providing the diagnostic clarity needed for researchers to implement targeted fixes.
Scale Evaluation: Collaborate with platform engineers to deploy evaluation frameworks across large-scale GPU clusters.