לוח משרות דרושים חשמל ואלקטרוניקה ברחובות, לחיפוש זה נמצאו 173 משרות

This is an opportunity to embark on an interesting and challenging adventure into the world of satellite communication which is undergoing a major disruptive revolution.

The LS includes Control and data processing HW, SW as well as Phy and Radio HW and FW, to construct a full communication system supporting DVB-S2X as well as other Radio and IP communication protocols.

Responsibilities
Landing station system validation activity including Phy, HW and SW validation.
Study system architecture and system requirements and take part in a test plan to address these requirements in collaboration with system engineering and other teams.
Define and write automatic test plans and test procedures for new systems and features.
Build test setups for fully automated regression as well as for manual tests.
Take active part, hands-on in team execution: integration and feature/product enabling, bring up and debug activities, regression automation test of satellite systems.
Record, investigate and analyze defects.
Investigation of root cause of test case failures and providing corrective action in conjunction with development teams.
Support Test Management tools and continuous integration methodologies
Data analysis and post processing of data collected.
Compilation of regular Test execution summary report with metrics.

Be part of a dynamic and motivated multi-national Physical Design team, taking part in developing a state-of-the-art Satellite SoC through the full life cycle: design to production. The chips include complex digital and analog modules. Some of the products are part of the next generation radiation hardened satellite modems. You will have access to best-in-class EDA design tools and will be working in leading edge process technologies.

Responsibilities:
Physical implementation of complex SoC, VLSI devices and Test Chips, integrating custom designs and 3rd party IP (Hard, Soft, IO, CPUs, DSPs, etc).
Full block level timing closure and manufacturing checks signoff including power planning and analysis.
Working alongside the Logic Design RTL team to develop timing constraints for implementation at block and chip level.
Insertion of DFT test structures and chip level integration, capture and simulation.
Jointly with management, build your career development and growth opportunities.