Required Design Verification - Intern
job requisition id
2604481
Your Team, Your Impact
Join a highly skilled development team, driving the development of our next-generation network switches. Our team is responsible for a wide range of IPs for switching products, from initial definition through architecture, design, and verification.
As an intern, you will learn switch architecture, design and verification development tools and modern methodologies. You will be doing hands-on development tasks and learn to become an experienced engineer. You will learn system verilog, UVM, Python, C++, using AI tools, and how to implement and verify complex features. You will investigate and implement new protocols and features and verify them to tapeout quality. We are looking for excellent students, able to handle complex problems, with excellent people relations and collaboration skills.
What You Can Expect:
Implement new features in design and verification.
Reach high-frequency, high-performance, and low-power targets.
Write a verification test plan using random techniques and coverage analysis.
Develop a complex object-oriented random verification environment using System Verilog/UVM.
Create tests and tune the environment to achieve coverage goals.
Own and debug failures in simulation to root cause problems.
Analysis/closure of code and functional coverage.
Use scripting languages to automate repetitive tasks and improve efficiency.
Requirements: What We're Looking For
Candidate pursuing a BS/MS (preferred) degree in CS/EE or related technical field(s).
At least two years before graduation.
Good understanding of object-oriented programming and digital logic.
Good people relations and ability to work in a team.
Excellent problem-solving ability.
This position is open to all candidates.