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21/06/2026
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are looking for an experienced DFT Design Engineer to join the DFT design team and develop the next generation DFT technologies.

As a design engineer in the DFT design team, you will participate in definition and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and sophisticated products, our DFT solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.

What you'll be doing:

In this position, you will be responsible for defining, coding and integrating sophisticated DFT components into various projects and using state-of-the-art technologies.

As a member of our DFT design team, you will participate in defining various DFT features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.

Strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.
Requirements:
What we need to see:

B.Sc. in Electrical Engineering or Computer engineering or equivalent experience.

5+ years of practical experience.

Exposure to rtl implementation and coding.

Familiarity with verification tools.

Strong debugging, problem solving and analytical skills.

Strong communication and social skills are required.

Ability to work in a geographically diverse team environment.

Self motivated, independent and target oriented.


Ways to stand out from the crowd:

Prior Design or Verification experience.

Experience in developing sophisticated design blocks.

Integration of design elements to large cluster or full-chip.

Experience in working with back-end on area, power and timing closures.

Scripting ability.
This position is open to all candidates.
 
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21/06/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
Our Chip Design group is looking for best-in-class Senior Design/ Verification Engineers to join our outstanding Silicon Engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in designing and verifying our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.



What youll be doing:

Design/ Verification for chip blocks/entities according to specifications, working under challenging constraints with a strong focus on performance.

Engage daily with all aspects of chip development, including Micro-architecture, Firmware, Design/ Verification and Integration.

Work with cutting-edge technology: developing the PCIe Gen7 standard and integrating it across all our chips (GPUs, CPUs, and NICs).
Requirements:
What we need to see:

B.Sc. or M.Sc. in Computer Engineering, Electrical Engineering, Communication Engineering, or equivalent experience.

5+ years of experience in Verification or Design.

High proficiency in English (both written and verbal).

Strong motivation to grow and excel.


Ways to stand out from the crowd:

Knowledge of the PCI Express (PCIe) standard.

Proven experience in Verification or RTL Frontend ASIC Design (Chip Design).

Experience with Specman.

Background in RTL microarchitecture (uArch) and coding.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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21/06/2026
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
Join our powerful Networking Silicon engineering team as a Synthesis Senior CAD Engineer! In this pivotal role, you'll be at the forefront of developing the industrys advanced high-speed communication devices, delivering outstanding efficiency and minimal latency. This is your chance to architect, build, and improve advanced RTL to PNR tools, flows and methodologies using the worlds latest process technologies. Be part of a group thats driving technology forward and pushing the frontiers of development.

What you will be doing:

Methodology Deployment: Design and refine sophisticated Synthesis flows to meet ambitious Power, Performance, and Area (PPA) objectives.

Partner closely with upstream Front-End Design and downstream Place & Route (P&R) flows development teams. Define boundaries, resolve design constraints, and bridge systemic execution gaps.

Develop robust and scalable scripts using Tcl/Python to improve Flow Turnaround Time (TAT). Integrate next-generation capabilities such as AI/ML automation into production runs.

Serve as a subject matter expert and trusted representative for adjacent project teams. Provide proactive support, deep-dive debugging of complex tool failures, and formal synthesis training to build teams.
Requirements:
What we need to see:

Academic Background: B.Sc./M.Sc. in Electrical Engineering, Computer Engineering, or a related technical field, or equivalent practical experience.

Core Synthesis Experience: 3+ years of hands-on experience in VLSI synthesis flows, with deep, proven expertise in Synopsys Fusion Compiler or Design Compiler (DC-Top/DC-Ultra).

Technical Skills: Strong proficiency in Tcl or Python scripting within a production-level CAD/EDA environment.

Attitude & Ownership: A highly enthusiastic, dedicated approach with a demonstrated "sense of ownership" to proactively step into process vacuums and drive complex tasks to completion.


Ways to stand out from the crowd:

Familiarity with synthesis, place and route, STA EDA tools from Synopsys (DC/FC/PT), Cadence (Genus/ Innovus/Tempus).

Experience in methodology definition / flow ownership of synthesis / Place and Route/ STA steps is an advantage.

Great teammate with strong ownership, self-learning skills, and the ability to work autonomously.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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21/06/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
We are looking for an excellent Firmware Engineer to join the Firmware team. The Firmware team develops groundbreaking networking features for AI, cloud, HPC and storage. We drive the data growth of the worlds biggest companies. With many hardworking engineers around the globe, the work environment is complex, results-oriented and fast paced. You will learn how a big software project is operated, maintained, qualified and released, and how Hardware and Firmware are developed.

What you will be doing:

Work closely with the architecture and different software and hardware design teams.

Implement new features for our NIC and Switch firmware.

Develop verification tests for advanced features in a highly complex and sophisticated Firmware testing environment.

Collaborate with multi-functional teams including chip design, board designers, Silicon, SW and program managers to debug any FW/validation issues.

Heavily involved with the early modeling and simulation required to produce our outstanding products including schematic and layout reviews on next generation board designs.
Requirements:
What we need to see:

University Bachelor's or master's Degree in Electrical/Computer Engineering, or equivalent experience.

Prior 4+ years of experience in Firmware.

Strong C/C++ and OOP capabilities.

Excellent Data analysis, debugging and problem-solving skills.

Strong understanding of digital design, computer architecture, Linux, drivers and CPU/GPU/SOC architecture.

Strong analytical, debugging and problem solving skills.

Motivated and independent with strong communication skills.


Ways to stand out from the crowd:

Coding and automation skills in scripting languages like Python.

Experience with RISCV architecture and verification.

Ability to multitask and prioritize in a fast paced environment.

Strong interpersonal and communication skills and ability to work effectively across different teams

Hands-on lab experience with board bringup, lab debug and lab tools (oscilloscopes, multimeters, logic analyzers).
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8702792
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21/06/2026
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are seeking a Networking Software Engineer to join our RDMA Transport Software team, driving the development of next-generation RDMA solutions for AI, cloud, HPC, and storage. You will research and develop innovative transport algorithms that push the limits of performance and scalability. You will work in a fast-paced, collaborative environment alongside talented engineers from around the world, supporting the data needs of the worlds largest enterprises

What you'll be doing:
Take part in research, design, and development of advanced RDMA transport mechanisms and algorithms, enhancing performance, reliability, and scalability.
Collaborate closely with hardware engineers, software developers, and system architects to align on project objectives and requirements.
Keep up with industry trends and emerging technologies, integrating new ideas and innovations into the development process
Requirements:
What we need to see:
Bachelor's or Master's degree in Electrical Engineering or Computer Science fields from a known institute.
5+ years of development experience
Knowledge with RoCE and/or InfiniBand, along with a background in RDMA development across software, firmware, or hardware.
Strong problem-solving skills with a hands-on approach, able to dive deep into the RDMA stack and solve complex issues.
Proficiency in C/C++ and embedded systems programming.
Fast learner possessing the ability to learn complex concepts in a fast-paced environment.
A can-do attitude and high energy with excellent collaboration, and social skills.

Ways to stand out from the crowd:
Background with data centers networking & storage workloads (advantage).
Familiar with RDMA, InfiniBand, or Ethernet technologies
Experience designing or tuning congestion control, flow control, or loss recovery mechanisms in high-performance networks.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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21/06/2026
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
The System-On-Chip (SOC) group is looking for a top physical design engineer with a curiosity about SOC design optimization, physical integration, chip build and assembly and verification. You should have real passion for methodologies and clock distribution solutions that enable SOC creation in the most optimized way. In this position, you will get the opportunity to build complex networking chips and directly contact unit-level owners, Physical Design, CAD, Package Design, Software, DFT and other teams.

What you'll be doing:

Designing and implementing SOC level clock requirements.

Daily work involves aspects of chip level design, including partitioning, CDC, trial synthesis, design quality checks.

Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, resolve design quality issues.
Requirements:
What we need to see:

B.SC. in Electrical Engineering/Computer Engineering.

3+ years of confirmed experience in chip design

Shown hands on physical design skills in clock distribution in tight multi power and timing/layout constrained products.

Proficiency in at least one common scripting languages like perl, python, bash, Tcl.

Phenomenal teammate.

Ways to stand out from the crowd:

Passion for quality. Experience with delivery back to RTL, to physical design, and other customers
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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21/06/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
We are now looking for a Senior Chip Design Engineer for the Switch Silicon group.

As a Chip Design Engineer at NVIDIA's Networking business unit, you'll join a group of passionate engineers to design and implement the next generation pioneering Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:

Work in a combined design and verification team which develops some of the switch silicon core units.

Build reference models, verify and simulate chip blocks/entities according to specifications.

Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW.
Requirements:
What we need to see:

Proven experience in RTL design or RTL verification.

4+ years of relevant experience.

Previous experience in networking - an advantage.

B.Sc. in Electrical Engineering or Computer Engineering, or equivalent experience.

A great teammate with good communication and social skills.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8702534
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18/06/2026
Location: More than one
Job Type: Full Time
We're looking for a Senior Data Scientist to join the AI cybersecurity team in the Security and Networking Architecture group. As a Senior Data Scientist youll have the opportunity to take an active part in the research and development of our world-class networking and data center security products. This role involves creative problem solving alongside engineering teams, and is key for the continued success of AI networking security.

What youll be doing:

Developing agentic AI systems for security, combining generative models, RAG, and tool-augmented reasoning to automate threat analysis and response workflows.

Optimizing and fine-tuning models for performance, scalability, and resource utilization, considering factors such as latency, efficiency, and cost.

Developing, implementing and improving models and algorithms across media types, whether time series, images, text, audio or video.

Leveraging data pipelines to efficiently process and transform large volumes of data for training and inference purposes.

Applying alignment techniques and parameter efficient fine-tuning to improve model performance.

Measuring and benchmarking model and application performance to drive improvements.

Driving the gathering, building, and annotation of domain specific datasets for benchmarking and training.

Collaborating closely with software and hardware engineers on new features and improvements. Participate in developing and reviewing code, design documents, use case reviews, and test plan reviews.
Requirements:
What we need to see:

MS/PhD with expertise in Computer Science, Computer Engineering, Electrical Engineering or related field with a focus on Deep Learning or Machine Learning.

5+ years of experience in deep learning and machine learning in a production environment.

Excellent Python programming skills, strong software design fundamentals, and experience leveraging coding agents in development workflows.

Hands-on experience with deep learning development frameworks and libraries (e.g. TensorFlow, PyTorch).

Experience with large scale production systems and pipelines, with a track record of developing production-grade models

Experience with agentic AI systems, agent frameworks, and evaluation of agent performance and reliability.

Strong algorithm development experience, with knowledge of inference optimization techniques such as model distillation, quantization, pruning.

Background with algorithms including zero/few-shot learning, self-supervised and unsupervised learning and generative AI models for synthetic data creation.

Experience with fine-tune / training LLM models

You are proactive, take full ownership of your deliverables, have a can-do approach, and are excited to learn, explore and apply your skills and creativity to some of the most challenging and rewarding problems in the field.


What will make you stand out from the crowd:

Strong software development experience.

Familiarity with GPU based technologies like CUDA, CuDNN and TensorRT.

Experience with tools for data processing and storage.

Security and networking background, with knowledge of security protocols, network architectures, firewalls, intrusion detection systems, and other relevant security and networking concepts.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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18/06/2026
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are seeking a passionate QA Engineer to join our FW testing team. This position will be part of our growing team, which enables our products to meet the industry-leading benchmarks of efficiency and quality. As a Firmware QA Engineer, you will be immersed in the latest advancements and actively contribute to developing world-class products. Your efforts will directly impact the performance and quality of our offerings, ensuring they consistently meet industry-leading standards.

We are looking for an ideal candidates who will be actively involved in testing industry-leading features in the FW sector, able to rapidly acquire new feature knowledge, conduct both manual and automated tests, and contribute to the development of automation systems.

What you'll be doing:
Review arch design and requirements documents for new features introduced in several domains like Switch/HCA/NVL/Linkx FW.
Design, develop, and perform tests for the new features, as part of FW GA or update releases.
Automate newly added tests in the existing automation framework, and add new capabilities and features to the framework.
Report bugs found during execution, assist with reproduction and debugs to understand root cause, verify bug fixes provided by R&D team, and raise if not fixed.
Conduct tests in various areas, including regression, performance, functional, and security. Keep track of testing progress and generate summary reports of testing activities.
Fully collaborate with different external teams like : :product marketing, R&D, and verification.
Define and build setups topologies for appropriate product coverage.
Requirements:
What we need to see:
Practical / BSc in Computer Science or Electrical/Electronics Engineering.
0-3 years of proven experience
Clear verbal and written communication, proficient in written and spoken English.
Self-reliant individual, capable of planning and carrying out tasks within their assigned area.
Personal: good interpersonal skills, quick learner, proactive, innovative, highly motivated, and committed.


Ways to stand out from the crowd:
Scripting skills and proven experience in Python or other programming languages
Proven experience in QA - methodologies, and test design.
Working in a fast-paced environment with multiple parallel running activities.
Knowledge/experience in Networking protocols.
Knowledge of Linux/Windows OS.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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18/06/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
We are looking for best-in-class Chip Design Verification Engineer to join our outstanding Networking Silicon Engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in verifying our ground-breaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What youll be doing:

Work as a Chip Design Verification Engineer as part of a combined design and verification team that develops front-end design for the Switch silicon, GPU and HCA.

Plan and Design Verification units/blocks according to Arch & Micro arch specifications under challenging constraints with high orientation to power, area, and performance.

Work closely with multiple teams within organizations such as Architecture, Micro-Architecture, and FW-interaction with organization-wide groups.
Requirements:
What we need to see:

Electrical Engineering B.Sc., Computer Engineering or other relevant engineering department graduate with high scores, or equivalent experience.

5+ years of experience in RTL verification. Less experienced engineers with high university grades will also be considered.

Experience in full and cluster-level verification is an advantage.

Self-motivated, ability to work independently and drive tasks to completion.

A great teammate with strong communication and interpersonal skills.


Ways to stand out from the crowd:

Knowledge in Specman, Verilog.

Knowledge in Networking.

Great interpersonal skills.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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18/06/2026
Location: Tel Aviv-Yafo and Ra'anana
Job Type: Full Time
We are looking for an excellent Firmware Design Engineer for NVIDIA FW PHY Group. The person will closely work with NVIDIA FW development, architecture, chip design teams and gain deep understanding of NVIDIA's Networking products and technologies. We have some of the most forward-thinking and hardworking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best chip design team in the industry!

What youll be doing:

Working on the most Ground breaking technology for building AI infrastructure.

Design and develop PHY-layer firmware for our latest networking devices, improving performance and reliability in our next-generation products.

Enabling new SerDes and physical linkup flows.

Work closely with the architecture, HW, and SW design teams.

Define implement and maintain FW algorithm to control the Silicon.

Develop and test FW on emulation & simulation environments during the Pre-silicon phase.

Debug and screen HW/FW/SW issues.

Take an active part in silicon bring-up and SW development phases.

Lead data-driven discussions about the product functionality and areas for improvement.
Requirements:
What we need to see:

B.Sc. or M.Sc. in Electrical or Computer Engineering.

3+ years of relevant experience.

Proficient programming in C.

Debugging experience and ability to investigate and triage difficult problems in embedded FW.

Good communication skills and the ability to work with people across several countries.

Ability to work with interrupts and dynamic environment with good spirit.

Excellent English verbal and written communication skills.


Ways to stand out from the crowd:

Proficient in Python and MatLab.

Good understanding of SerDes operation.

Experience with developing the physical layer of communication protocols.

Knowledgeable of Hardware/Software Development Process.

Strong collaborative and interpersonal skills, with an ability to successfully guide and influence.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8701266
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
18/06/2026
Job Type: Full Time
We are seeking an experienced Security Architect who has experience in confidential computing and attestation systems. The ideal candidate should have deep expertise in at least one leading confidential compute architecture and ideally in PCIe support around TDISP, IDE, SPDM. Strong knowledge of general system security, virtualization and hardware-enforced isolation primitives is essential.

What you'll be doing:
Lead, research, design, develop, and implement solutions for next-generation confidential computing network devices.
Develop novel hardware isolation mechanisms to provide defense in depth in the SoC.
Collaborate with external and internal hardware and software teams to implement and deliver the architecture.
Architectural modeling, validation, microarchitectural definition, and developing proofs-of-concept for secure platforms.
Requirements:
What we need to see:
BSc, MSc, or PhD in Electrical Engineering, Computer Science, or Computer Engineering, or equivalent experience.
5+ years of experience.
Background in confidential computing, attestation, virtualization, and operating systems security.
Programming and debugging fundamentals across languages such as Python, and C/C++.
Strong communication skills and a genuine passion for working together as a team are vital.

Ways to stand out from the crowd:
Demonstrated security research experience and publications in top security conferences.
Experience with AI tools for architectural modeling.
Architectural background in hardware and software systems codesign.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8701238
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18/06/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
Youll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. Join our team as a Senior Power and Performance Architect - Networking, influencing the future of our network systems.

What you'll be doing:
Develop, model, and validate groundbreaking power and performance optimization techniques for network fabrics, components (NICs, Switches), and systems. Collaborate closely with cross-functional teams including silicon design, system architects, software/firmware engineers, performance analysts, thermal engineers, and AI researchers to ensure end-to-end power and performance optimization. You will determine strategies that successfully implement flawless performance and power efficiency in our ambitious projects!
Requirements:
What we need to see:
BSc or MSc or equivalent experience in Electrical Engineering, Computer Engineering, Computer Science or a related field.
5+ years of relevant experience in network architecture, design, or performance analysis.
Solid understanding of power consumption dynamics in network hardware (NICs, switches, cables) and systems.
Proven experience in network architecture and design, particularly for large-scale systems (Data Center, HPC, AI Clusters).
Strong understanding of network protocols (Ethernet, InfiniBand, RoCE, TCP/IP) and their impact on performance and efficiency.
Demonstrable expertise in network performance analysis, bottleneck identification, and tuning.
Familiarity with the characteristics and network demands of AI/ML workloads
Utmost passion for attention to details in design and a high focus on design quality, particularly concerning power/performance trade-offs.

Ways to stand out from the crowd:
Advanced degree or equivalent experience in a related field.
Proven dedication to system-level power/performance trade-off analysis, especially in distributed computing or large-scale network environments.
Experience in power modeling, measurement techniques, or relevant tools for network components and systems.
Proficiency with network simulation tools (e.g., ns-3, OMNeT++, proprietary tools) or performance modeling frameworks.
Understanding of silicon-level power characteristics and optimization techniques.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8701230
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18/06/2026
Location: More than one
Job Type: Full Time
We are seeking a technical leader to define, craft, implement, and guide firmware architecture for reliability, availability, serviceability, and power management across next-generation Networking products and platforms. You will take a strong hands-on role, working with hardware, firmware, software, validation, customer engineering, and external partners to build robust, diagnosable, power-efficient systems for large-scale deployments.

What you'll be doing:

Define platform-level firmware architecture for RAS and power management across SoCs, accelerators, DPUs, servers, embedded systems, and data center platforms.

Own error detection, classification, containment, recovery, escalation, and reporting architecture.

Define firmware architecture for power sequencing, power states, reset flows, thermal and power fault handling, idle management, and recovery from power-related failures.

Create firmware specifications for hardware error handling, health monitoring, crash capture, telemetry, diagnostics, debug data, and field serviceability.

Define interfaces and contracts between firmware, hardware, operating systems, BMCs, management controllers, platform software, and cloud/service infrastructure.

Drive architecture reviews, tradeoff discussions, failure-mode analysis, validation strategy, and long-term RAS and power management roadmap planning.

Establish standards for error logs, event schemas, telemetry flows, recovery policies, service diagnostics, and production debug infrastructure.

Guide engineering teams through implementation, validation, silicon bring-up, platform integration, and production deployment of RAS and power management features.

Analyze customer and field failures, identify architectural gaps, and feed lessons learned into future platform designs.
Requirements:
What we need to see:

BSc, MS, or PhD in Electrical Engineering, Computer Science, Computer Engineering, or equivalent experience.

7+ years of relevant experience in firmware, platform architecture, embedded systems, or low-level systems software.

Deep understanding of RAS principles, fault modeling, error containment, recovery policies, diagnosability, and serviceability requirements.

Experience architecting firmware for complex hardware platforms such as SoCs, accelerators, DPUs, servers, networking devices, or embedded systems.

Strong knowledge of power management concepts, including power sequencing, reset architecture, thermal and power fault handling, power state transitions, and platform recovery flows.

Familiarity with boot firmware, UEFI/BIOS, BMC, embedded controllers, RTOS, embedded Linux, or platform management stacks.

Strong understanding of hardware/software interfaces, registers, interrupts, telemetry paths, debug infrastructure, and firmware-to-hardware contracts.

Programming and debugging fundamentals across languages such as C/C++, Python/Perl scripting, Verilog, assembly, or RISC-V assembly.

Ability to lead cross-functional architecture discussions and drive alignment across hardware, firmware, software, validation, product, and customer-facing teams.

Excellent communication skills, strong technical leadership, and a real passion for working collaboratively.


Ways to stand out from the crowd:

Experience with PCIe AER, CXL RAS, memory RAS, ECC/parity, accelerator RAS, networking RAS, high-availability systems, or large-scale data center platforms.

Knowledge of ACPI, SMBIOS, UEFI, PLDM, MCTP, Redfish, IPMI, or cloud telemetry systems.

Experience with power/thermal fault handling, dynamic power management, platform power sequencing, low-power states, or autonomous recovery mechanisms.

Background in silicon bring-up, platform validation, production diagnostics, or customer failure analysis.

Prior technical leadership experience as a firmware architect, principal engineer, platform lead, or domain owner.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
8701223
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
18/06/2026
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
Are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? Our Engineering team works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. We are looking for an experienced DFT Engineer to join the ATPG team. The position includes taking part in development of the next generation DFT technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.



Working on the most advanced technologies and complex products, our DFT solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. If you find groundbreaking Technologies, and next generation products interesting, then this is the team for you. Take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!



What youll be doing:

You will be in charge of state of the art Design for Test/ATPG flows and implementation.

Take full ATPG ownership end to end on a project, from Arch & planning to pattern generation, verification and post Silicon bring up and diagnosis.

Inventing and maintaining automation flows that provide the short test time to production.
Requirements:
What we need to see:

5+ years of hands on DFT/ATPG experience knowledge & technical experience in DFT ASIC Design and in ATPG tools.

Strong programming skills in scripting languages.

BSc. in Electrical Engineering or Computer engineering.

Quick learner, proactive and self-motivated, eager to learn and contribute, sense or ownership, commitment, and responsibility.



Ways to stand out from the crowd:

Knowledge of DFT including scan, BIST, on-chip scan compression, fault models, ATPG, and fault simulation.

Experience in Mentor TestKompress ATPG tool and retargeting flow.

Programming languages: TCL, PRL, Phyton & Unix shell scripts.

Experience with ATE and Silicon bring-up.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8701217
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