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We are looking for best-in-class Senior Chip Design Verification Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency!

Come and take a significant part in designing and verifying our groundbreaking and innovating new chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What you'll be doing:

Take a crucial part in developing our next-generation chip controller

Design and verification with challenging multi-discipline context

Take part in the development of all our networking and GPU networking chips and systems.

We are seeking a sharp, innovative, and hands-on Architect to help shape the future of LLM inference at scale. Join our dynamic E2E Architecture group, where we build cutting-edge systems powering the next generation of generative AI workloads. In this role, you will work across software and hardware domains to design and optimize inference infrastructure for large language models running on some of the most advanced GPU clusters in the world.

Youll help define how AI models are deployed and scaled in production, driving decisions on everything from memory orchestration and compute scheduling to inter-node communication and system-level optimizations. This is an opportunity to work with top engineers, researchers, and partners across us and leave a mark on the way generative AI reaches real-world applications.

What Youll Be Doing:

Design and evolve scalable architectures for multi-node LLM inference across GPU clusters.

Develop infrastructure to optimize latency, throughput, and cost-efficiency of serving large models in production.

Collaborate with model, systems, compiler, and networking teams to ensure holistic, high-performance solutions.

Prototype novel approaches to KV cache handling, tensor/pipeline parallel execution, and dynamic batching.

Evaluate and integrate new software and hardware technologies relevant to Core Spectrum-X technologies, such as load balancing, telemetry, congestion control, vertical application integration.

Work closely with internal teams and external partners to translate high-level architecture into reliable, high-performance systems.

Author design documents, internal specs, and technical blog posts and contribute to open-source efforts when appropriate.

Were looking for a Hardware Qualification Engineer to join our Hardware R&D team in Tel Aviv. In this role, you'll ensure our hardware systems perform reliably under real-world conditions.
Youll work closely with our system, software, and validation teams to design and execute comprehensive qualification test plans and legal qualification requirements. Your insights will directly impact the quality, robustness, and performance of cutting-edge control systems.
Key Responsibilities:
Define and implement system-level hardware qualification procedures based on in-depth analysis of circuit and system designs.
Design and build complex test setups, integrating our hardware with advanced measurement tools.
Run and analyze qualification testsstress, thermal, performance, and edge cases.
Review test data to identify anomalies and assess hardware readiness.
Collaborate with engineering teams to communicate findings and support root-cause investigations.
Maintain clear, detailed documentation of test methods, configurations, and results.
Work with vendor laboratories to certify our systems to CE, FCC and other international requirements.

We are looking for a seasoned Electronics Engineer with over 5 years of hands-on experience in analog circuit design and power supply engineering. In this role, you will focus on developing and refining analog circuitssuch as amplifiers, filters, and DACs operating from DC to 2GHzand power supply solutions across various topologies.
As the go-to person in electronics, youll work as a key contributor and technical expert, collaborating closely with our hardware teams in Denmark and Israel, as well as operations during the NPI phase.
Key Responsibilities:
Analog Circuit Development:
Design and optimize analog circuitry, including op-amps, filters, and signal generation modules (DACs) covering frequencies from DC up to 2GHz and above.
Power Supply Engineering:
Develop robust power supply designs across various schemes (buck/boost converters, LDOs, switching regulators, etc.) that meet high-performance standards.
Lab and debug experience:
Experience in working in labs, measuring and debugging electronics.
Simulation & Design:
Utilize Altium for PCB design and LTspice for circuit simulation to validate and refine your designs.
Design for Manufacturing & Test (DFM/DFT):
Incorporate DFM and DFT best practices to ensure reliability, manufacturability, and scalability across many channels in compact form factors.
Performance & Compliance:
Ensure designs meet stringent low-noise requirements and EMI/EMC compliance for high-performance applications.
Cross-Functional Collaboration:
Work closely with hardware teams in both Denmark and Israel, and engage with operations during the NPI process to ensure seamless integration of your designs.
Technical Expertise:
Act as the electronics subject matter expert within the team, providing technical sparring and review to peers.

We are looking for NPI Engineer who will join the operation team and help us scale onwards!
The NPI product leader will be responsible for transitioning new products from early stage development to production level till field deployment processes. Work with cross functional teams ranging from HW designers, systems engineers, marketing and operations teams and participate in the complete product life cycle from development through build prototype until handing off the product to sustaining engineers.
The NPI product leader will manage all engineering related activities of QMs new products. The NPI PL will have a full responsibility on the overall operational activities to ensure qualified manufacturing readiness of new products.
Responsibilities:
Lead cross functional teams to execute the NPI process within the operations group.
Set an overall Operational NPI plan, Set Ops KPIs, Track and follow project progress, manage risk and report accordingly.
Define the NPI methodologies, interfaces, and process within the operation matrix to ensure smooth product introduction
Providing engineering leadership for the definition and scoping of NPI projects for all aspects of manufacturing and transitioning of projects to Manufacturing for project implementation and subsequent operation.
Ensure Design for Manufacturing guidelines are well implemented in the product design and validate implementation impact on product quality
Overall accountability of production data integrity including: BOM, production documentation, jigs and tools, product regulation.
Establishing and documenting process specifications that ensure manufacturing operations will meet product capability and quality expectations.
Analyze and recommend improvements to all production processes and methods to facilitate cost reduction and quality improvement through engineering change requests
Prepare plans for all NPI projects and coordinate with all stakeholders to ensure a good quality product represent the operations in the product life cycles gates
Serve as a technical mentor to contract manufacturing during NPI process

We are now looking for a Senior Chip Design Engineer for the Switch Silicon group.

As a Chip Design Engineer in our Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state of the art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:

Work in a combined design and verification team which develops some of the switch silicon core units.

Build reference models, verify and simulate chip blocks/entities according to specifications.

Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW.

We are looking for RF Integration engineer to join our Tel-Aviv RND team. As part of the role, you will characterize the performance of QM analog front end including its sensitivities and interoperability with various QUBIT types; take part in proof of concept and definition of next gen QM systems HW; will take care to validate its quality and reliability.
By joining us, youll have the chance to be involved from the early stages of architecture & design, through the development and testing phases up to end-to-end integration within QM products.

We are seeking an exceptional architect to join our Architecture team and help shape the future of quantum computing. As quantum computers near production scale, were uniquely positioned to define the system and software architecture that will power the next generation of computing.
In this role, you will be responsible for end-to-end definition of new capabilities, from the quantum programming languages through the compilation processes to the pulse processor. This position demands deep expertise in software architecture across all levels, an ability to work closely with logic design teams, a strong ability to learn and adapt, and a passion for becoming an expert in quantum computing. Youll collaborate closely with Product, R&D, and Research teams to transform ideas into technical reality.
Responsibilities:
Define system-level architecture and features, and provide comprehensive specifications for R&D implementation
Design quantum control programming languages and representations optimized for our unique hardware and application requirements
Define architecture in our unique pulse processor end-to-end, from language and software interface to logic capabilities
Collaborate cross-functionally across Software, Compiler, Logic Design, and Quantum Software teamsfrom concept to production
Work hand-in-hand with Product and Research teams to translate high-level requirements into concrete architecture plans
Development of Proof-of-Concepts for new software capabilities and features

We are seeking a highly skilled Hands-On Engineer to join our Integration Team, ensuring seamless integration of multi-layered systems. This role requires close collaboration with cross-functional teams to debug, validate, and integrate complex interfaces while ensuring end-to-end functionality.
Key Responsibilities:
Integration of multi-disciplinary systems, ensuring smooth operation across different layers.
Debug and troubleshoot issues arising in the integration process.
Develop integration and validation tools.
Collaborate with architecture, logic design, verification, compiler, and embedded teams.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our companyusers worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
our company's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of our company AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
As a Power and Signal Integrity Engineer, you will be responsible for the design and characterization of signal and power integrity of our IC designs. You will design the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives.
You'll set up methodologies, perform simulations, silicon characterization and correlations to ensure our IC designs meet systems design budgets and achieve the highest performance. You will work with systems architects, ASIC design, systems engineers, and partner cross-functionally with teams and external vendors/partners.
The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users , Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Design and optimize power distribution networks (PDN) across chip, package, and board levels. This includes managing power/ground planes, decoupling capacitors, and power gating strategies.
Conduct both pre-layout and post-layout power integrity simulations to analyze power and ground noise (SSN/SSO), voltage drops (IR drop), and electromagnetic interference (EMI).
Implement and verify low-power design methodologies, such as multi-voltage designs and clock gating, using power intent formats like UPF/CPF.
Generate precise electrical models (e.g., S-parameters, SPICE models) for components such as packages, PCBs, and connectors for use in simulations.
Execute lab measurements utilizing test equipment like oscilloscopes, Vector Network Analyzers (VNA), Time Domain Reflectometers (TDR), Spectrum analyzers to validate simulation outcomes and debug signal and power-related issues on silicon prototypes and boards.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will use your ASIC design experience to be part of a team that develops the ASIC SoC from Plan of Record (POR) to Production. You will be creating SoC Level micro architecture definitions, RTL coding and will do all RTL quality checks. You will also have the opportunity to contribute to design flow and methodologies. You will collaborate with members of architecture, software, verification, power, timing, synthesis dft etc. You will face technical tests and develop/define design options for performance, power and area.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Participate in architecture feedback.