לוח משרות דרושים חשמל ואלקטרוניקה בתל אביב יפו

We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Define the System on a Chip (SoC)/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power closure and Application-specific integrated circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SoC level verification.
Communicate and work with multi-disciplined and multi-site teams.

We're hiring! production technician cut to fit
location: tel aviv
A cutting-edge company and global leader in material science, is looking for a production technician to join our dynamic team!
?what youll do:
laser cutting of advanced materials
gluing and soldering of electrical components
conducting quality tests
preparing products for shipment
join us and be part of something smart, innovative, and truly global.
think youve got what it takes? apply now.

We are now hiring a Senior Deep Learning Researcher, with experience, skills, and data-driven reasoning to take a leading role in solving our core data science challenges. To meet these, you will be expected to exhibit outside-of-the-box thinking and leadership skills, while collaborating with the engineering, hardware, data, and field application teams.

As a member of our ML team, you will tackle unique challenges in the domain of Optical Fiber Sensing. Fiber Sensing measures the acoustic signal along an optical fiber and is interpreted as a continuous acoustic signal originating from tens of thousands of microphones spanning hundreds of kilometers. You will cultivate a deep familiarity with this domain and research novel Deep Learning approaches that address domain-specific challenges in detecting, classifying, and tracking spatiotemporal events.

Responsibilities:
Spearhead deep learning projects that tackle real-world challenges, pushing the boundaries of what is possible.
Harness advanced data analysis and visualization tools to gain insights from complex real-world data.
Proactively seek new directions for tackling hard-to-crack problems, including devising real-world experiments and data collection, and collaborating with fellow physicists and engineers.
Develop multidisciplinary expertise in physics, engineering, and other adjacent expert fields.
Stay at the forefront of your field with continuous learning and in-depth research into cutting-edge topics.
Thrive in a dynamic setting where rapid prototyping and fast-paced project turnovers are the norms.

We are looking for the best minds and spirits to join us in our journey. We know our product is only as great as the individuals building the hardware and software and harnessing data for worthy causes. Being a great team member means being eager to learn and grow, able to challenge and accept being challenged, and working for the team and the product with enthusiasm and passion.

The Senior Data Scientist is a unique position, bringing CTO-grade capabilities to the incubation and initial launch process of our products. As the data scientist you understand the physics underlying the product, devise the mechanism of its operation, work together with R&D to develop it, and then analyze results coming from customer installations. Your data analytics insights feedback into the development cycle, while your quick fixes to the AI models enable rapid response to product gaps discovered.

The Senior Data Scientist at will report to the VP Product.

Responsibilities:
Develop deep expertise in our Photonics technology stack and its applications.
Collaborate with expert colleagues in AI, data analytics, physics, weather services, and satellite imagery.
Gain a deep understanding of the physics behind each product feature, develop the operational methodology, and collaborate with R&D to design, build, and deploy it.
Work closely with R&D to translate product concepts into deployable features.
Analyze data from real-world customer deployments to identify product gaps and refine AI models.
Rapidly implement AI-driven improvements to enhance customer experience and inform future product iterations.

We are now hiring a leader for the Physics group, who likes to see the whole picture, to take part in developing the core technology for our fiber-sensing platform.

Responsibilities:
Full responsibility for the hardware development of the product.
Managing a team of four Physicists.
Managing the teams of electrical board, mechanical and thermal design.
50% Hands-on.

The Director of AI is responsible for leading all aspects of Deep Learning, Machine Learning, and Signal Processing research for our products. The AI team supports all of our market segments, including power lines, border security, oil and gas pipelines, and more. This leadership role drives the development and implementation of complex algorithms across our product portfolio and plays a key role in enhancing our companys ability to interpret seismic and acoustic signals captured by our unique fiber sensing technology.

Were seeking a visionary leader who is an expert in deep learning and passionate about pushing the boundaries of our technology. The ideal candidate will bring infectious enthusiasm to the team, inspire innovation, and pursue excellence. They must be able to articulate complex concepts clearly, make decisive choices, and focus on key product capabilities with a forward-thinking strategy.

Responsibilities:
Lead and inspire three high-performing algorithm teams by setting clear goals, creating effective work plans, and conducting regular progress reviews.
Implement necessary organizational adjustments to optimize team dynamics and ensure seamless alignment with company objectives.
Foster a team culture that emphasizes professionalism, accountability, collaboration, and quality.
Lead the development of advanced AI models tailored to our market segments. Take full ownership of designing, training, and deploying AI components for cloud data pipelines and edge computing services.
Establish a robust framework for continuous updates and field integration, driving consistent improvements in KPIs and model generalization.
Clearly articulate the capabilities and value proposition of our AI models to stakeholders, including technical customers and executives. Provide insightful analysis of risks and opportunities to support critical company decisions regarding market strategy and product development.
Foster close relationships with our data engineering, edge computing, optical systems, project management, and product teams. Lead the effort in building a scalable, future-proof infrastructure that supports efficient development, ensures operational continuity, and facilitates the rapid scaling of AI initiatives.

We are seeking a highly motivated Chip Design Architect to join our team of experts and help shape the future of high-performance computing. Our next-generation Infiniband and NVL switches will be at the forefront of connecting and powering the world's most advanced compute clusters, from supercomputers used in AI research to high-performance clusters used in industries such as finance and research labs. As a Chip Design Architect at our company, you will have the opportunity to work on some of the most cutting-edge technology and help to drive the innovation of our next generation of switches that will be used by top researchers and engineers around the world. The products you'll develop will be integrated in many leading-edge compute clusters, and supercomputers, and you'll be part of a team with a strong track record of success.

What you will be doing:

Collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and hardware teams, to ensure the successful execution of the project.

Define the HW boot, clock and Reset architecture for Switch ASIC.

Develop slow-speed interface architecture specifications and design guidelines, conduct trade-off analysis for different architecture options, and oversee the implementation of the chosen architecture by the chip design / FW / SW teams.

With the growing demand for traffic bandwidth in datacenters, efficient physical high-speed communication becomes a crucial part of the development of silicon ASCs that serve networking infrastructures. We are looking for a PHY (Physical Layer) Architect for our Architecture team. We are positioning you to a key role to face this challenge and become part of our team, so we can continue developing the best devices in the industry.

Our networking architecture group is seeking for a highly skilled, leading engineer to explore, and define the Physical layer of our products. As a lead engineer, you'll be responsible to define and drive features and have responsibility on the Physical layer architecture. The role will include definition of both the hardware features and the firmware/software that is involved in operating the physical layer communication, with emphasis on the former. We are searching for hardworking, enthusiastic, engineer which has both highly technical skills as well as good personal skills, in order to be able to lead cross groups activities.

What you will be doing:

Lead projects across team, starting from processing requirements and definitions from customers and translating those into detailed technical specification for firmware architecture, system embedded software, user interface and high-level design.

Supervise the implementation of projects by team-leaders / developers / QA, participate in low level design reviews, QA test plans reviews, and keep track of changes and handle obstacles.

Define the architecture of implementing physical layer standards into our ASIC devices.

Involved in standard bodies activities and definition of next generation protocols.

Define features for the phy layer, to exploit interoperability between different generations of communication.

Be involved in product definition and the high-speed protocols that the networking devices will support.

Work closely with multi-functional teams - design, backend, system, marketing, firmware, driver, etc. Provide architecture definitions and as a result converge on key design decisions.

Become focal point for our physical layer networking communication devices.

We are looking for best-in-class Physical Design Team lead to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you will be doing:

Leading and mentoring Physical Design-Backend team.

Physical design of blocks/top-level according to specifications under challenging constraints targeting for the best power, area, and performance.

Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.

Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.

Taking part inflows development.

Take part in project definition towards POR, close interaction with other domains such as FE, ARCH.

We are looking for best-in-class Chip Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in designing and verifying our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What you will be doing:

Join Beer-Sheva/Tel-Aviv group, working on verification/design in the field of encryption accelerators.

Verification for chip blocks/entities according to specifications under challenging constraints and with high orientation to power, area and performance.

Daily work will involve verification and might involve any or all aspects of chip development including design and micro-architecture.

Work closely with firmware and other groups around the globe.

Work mode: Hybrid home-office.

We are looking for best-in-class Physical Design Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

Design of silicon Interposer according to specifications under challenging constraints targeting for the best power, area, and performance.

Be exposed and work on a variety of challenging designs (including complex chip designs). Resolving complex FloorPlan and congestion problems.

Daily work involves all aspects of physical design in interposer layout till GDS and Top Die Floor Planning including Bump design

Taking part in flows development.

We are looking for an experienced DFT Engineer to join an exceptional team of DFT experts to develop the next generation DFT technologies.

As a DFT engineer at the networking group, you will participate in definition and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and sophisticated products, our DFT solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.

What you'll be doing:

In this position, you will be responsible for defining, coding and integrating sophisticated DFT components into various projects and using state-of-the-art technologies.

As a member of our DFT design team, you will participate in defining various DFT features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.

Strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.

We are looking for an experienced engineer with a strong background in ASIC design to join our Chip Design Methodologies & Shared Code team. This team is responsible for establishing design methodologies, developing shared code, providing design guidance, and driving the adoption of new technologies. It plays a key role in ensuring chip design teams operate efficiently and adhere to best practices. This role offers an exciting opportunity to think innovatively and make a significant impact within a dynamic, technology-focused organization.


What You'll Be Doing:

Develop shared design code and solutions to be widely used by the chip design team.

Develop groundbreaking methodologies and innovations to create flawless experience for chip design engineers.

Collaborate with chip design peers and stakeholders across the teams to understand existing problems and form the best solutions and methodologies.

Collaborate with design automation team to provide end-to-end solutions that combine design, verification, simulation and automation.

Get in touch with EDA vendors to learn about cutting-edge tools/technology and apply them into our development process.

Develop training sessions.