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In this role, you will work with system teams and the CPU Architecture team to develop an understanding of the CPU, SoC, performance metrics, benchmarks/measuring tools, and available optimization knobs. You will define methods and technologies to model CPU performance at different accuracy levels by supporting architectural explorations and decision-making. In addition, you will correlate performance projections with measured post-silicon data.

Responsibilities
Design, develop, test, deploy, maintain, and improve CPU software modeling and other software tools.
Manage individual project priorities, deadlines, and deliverables.
Collaborate with hardware and software CPU architecture teams, SOC performance modeling team, and other Google Software teams.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-specific integrated circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

we are looking for a Senior Silicon DFT Lead, Google Cloud
Responsibilities
Lead and execute DFT activities in the design, implementation, and verification solutions for Application-Specific Integrated Circuits (ASIC).
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage a DFT team planning, deliverables, and provide technical mentoring and guidance.
Lead DFT execution of a silicon project, planning, execution, tracking, quality, and signoff.

we are looking for a Hardware Emulation Engineer, Google Cloud
Responsibilities
Help to maintain and upgrade emulation infrastructure and act as a primary interface to emulation vendors.
Explore emulation methodologies, gather feedback from the team, and implement emulation workflows and methodologies.
Create tooling and automation to support emulation Electronic Design Automation (EDA) tools, licensing, and job management in infrastructure.
Support emulation team members in debugging hardware, tooling, and project specific issues.
Help bring up external interfaces (e.g., USB, Peripheral Component Interconnect Express (PCIe), Ethernet, etc.) on the emulation platforms, and create test cases for tool issues encountered in the emulation compile and runtime flows.

we are looking for a Junior SoC IP Design Engineer, Google Cloud
Responsibilities
Define the SoC/Block level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
Perform RTL development (coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power closure and ASIC silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

As a Technical Program Manager for Silicon Development, you will use your technical and management experience to lead the development and execution of complex, multidisciplinary SoC projects. You will plan programs and manage their execution from early concepts through development to tape-out and production. You will collaborate closely with architecture, design, verification, physical implementation and manufacturing teams throughout the SoC execution life cycle. This includes making technical decisions for the chip designs and methodology, driving project schedules, identifying risks and communicating them to all stakeholders, and managing partner teams.

Responsibilities
Plan, coordinate, and deliver custom silicon products.
Assess complexity and scope out the project, generate task lists, build a project timeline and work with the teams to make it into reality.
Lead the data-driven schedules and milestones, track the progress, proactively identify potential future issues, and identify mitigations with the team leaders.
Drive technical, budgetary, and schedule trade-off discussions with cross-functional teams.
Manage project execution and issues through design, development, test, manufacturing, deployment and sustaining activities for silicon and hardware products.

we are looking for a Design Integration Engineer, Google Cloud, Networking
Responsibilities
Define and implement solutions for design, integration and verification problems using in-house and external technical solutions or tools. Ensure chip quality by implementing best practices and implementing quality control measures.
Participate in project development and convergence with the highest quality, and manage issues as they arise through design and implementation.
Connect between RTL design, physical design, Design for Test (DFT), external IPs and SoC while maintaining project priorities.
Maintain project infrastructure and stability.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Develop DFT strategy and architecture (e.g., Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG), hierarchical DFT).
Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality.
Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic Built-In Self Test, Test Access Point (TAP) controller, clock control block, and other DFT IP blocks.
Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces.
Document DFT architecture, test sequences, and boot-up sequences associated with test pins.

Required Motion Control Engineer
This is a hands-on role within our Robotics R&D Group. The Motion Control Engineer will be responsible for the development and maintenance of control systems for our robotic fleet. The control team is an integral part of a multidisciplinary group that collaborates on the design of robots for our fulfillment centers. The environment is fast-paced and requires investigating issues and faults from real-world sites and designing innovative solutions to complex, multi-domain problems.
What you'll do:
Control System Development:
Deliver reliable, operational control systems for robotic operation
Implement control algorithms across platforms such as PLCs (CODESYS) and embedded systems (STM32 MCU running FreeRTOS)
Handle both low-level embedded and high-level control systems
Problem Solving & Debugging:
Analyze and resolve complex control challenges
Conduct remote debugging and issue resolution
Diagnose and resolve system-level issues using a mix of analytical and hands-on approaches.
Continuously improve control performance through tuning, profiling, and iterative refinement in lab and live environments.
Cross-functional Collaboration:
Work closely with mechanical, electrical, embedded, software, and testing engineers
Collaborate on designing integrated robotic control architectures.

We are looking for a highly experienced and motivated Engineering Product Leader to join our Operations Engineering Team.
This role combines deep expertise in electrical and component engineering with strong product leadership and configuration management responsibilities.
This is a multidisciplinary and hands-on role, responsible for supporting the transition of new products from development into production (NPI), managing electrical components and designs, and maintaining configuration integrity through the PLM system, close collaboration with R&D, Procurement, QA, and Production teams, as well as with EMS/ODM suppliers and external manufacturing partners.
The role includes full responsibility for the administration and configuration management of the PLM system (Teamcenter), ensuring accurate product data management, BOM control, revision and change management, and supporting the Operations team as the PLM system administrator.
What youll do:
Engineering Product Leader / Electrical Engineer
Take full ownership of product engineering responsibilities starting from the NPI phase through production ramp-up and lifecycle support (subcontractors and EMS/ODM manufacturing partners)
Collaborate and interface closely with R&D engineers during early development stages to ensure manufacturability and technical alignment.
Manage all engineering activities related to product introduction, engineering changes, and production support, without direct development responsibility.
Review and update electrical schematics and drawings, provide technical input for troubleshooting and improvements.
Collaborate with R&D on design-for-manufacturing and testing (DFx) considerations.
Component Engineering (Primary Focus):
Responsible for all aspects of electrical component engineering across the company.
Define, select, qualify, and approve electronic/electrical components for new and existing products.
Manage component library and BOM structures in the PLM system (Teamcenter).
Evaluate EOL (End of Life), lead-time risks, and propose alternates or cost-saving solutions.