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We are looking for a Verification Engineer who embodies ambition and positivity, who can passionately take ownership of their responsibilities, collaborating effectively with remote teams to not only meet but exceed our objectives and fulfil the evolving needs of our expanding customer base.

The Verification engineer we look for will be a highly talented and motivated person, who is a real team player and can collaborate closely with engineers from other disciplines and quantum physicists.

Responsibilities:

Practicing the full range of verification aspects
Creating a verification environment from scratch (drivers, monitors, coverage...)
VIP (DDR/PCIe/AXI) integration
Defining verification sequences via a complex control-flow constraint set
System understanding of a full-stack product with strong HW-SW coupling
Reference model integration
Test plan definition
Defining verification flows and creating the proper infrastructure to support it

We are looking for a super talented engineer to join our team and build architectural model of a quantum control system.

We are looking for a motivated person, who is a real team player and can collaborate closely with engineers from other disciplines and quantum physicists

Responsibilities:

Working in all fronts high-level architectural solutions to low-level design constraints
Working across multiple teams and methodologies
Designing a complex IP to be used both internally by various R&D teams and externally for our customers as a stand-alone product
Designing a flexible and integration-able model to allow referencing from various programming languages (UVM, Java, Python, Kotlin and C++) as well as coupling it to a behavioral quantum simulator

As a Tech Leader in the AI Algorithm Engineering group, you will play a pivotal role in both managing end-to-end AI research and development efforts and hands-on involvement in key-initiatives. Your responsibility will include design, implementation, guidance and mentoring for team members, and representing the AI considerations in cross-team discussions. You will leverage your extensive experience to lead multiple AI projects, and will be a key figure in leading successful execution and in finding creative solutions to difficult bottlenecks, across data, AI, engineering and product considerations.
Responsibilities:
Lead the design, development, and implementation of accurate and robust AI algorithms for medical data with a hands-on approach.
Collaborate with cross-functional teams, including data scientists, software engineers, product managers and clinical data experts, to ensure AI considerations have a profound impact on R&D and Product decisions across the projects.
Design and conduct research and experimentation to improve algorithm performance and accuracy.
Stay at the forefront of the latest advancements in AI and machine learning, particularly in the medical domain, and drive their adoption within the team.
Oversee multiple projects, ensuring successful execution, timely delivery and alignment with product and business objectives.
Provide strategic direction and technical mentoring to elevate the capabilities of the AI team.

Be part of a team to verify complex digital design blocks at subsystem level or full chip level by fully understanding the design specification and interacting with design engineers to identify key verification scenarios.
Create and enhance constrained-random verification environments using UVM SystemVerilog or create complex multi core based C tests using reusable C test libs.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

Perform thorough Lab characterization/Validation of Serializer/Deserializer (SERDES) IPs, such as PCIeG6 PHYs.
Write Inhouse tools/scripts to characterize the IP.
Manage bench test, debug, and characterization of analog/mixed signal on-chip circuitry (PLLs, Clocks, Data Converters and various I/O Interfaces).
Manage the development of benchtop electrical tests exercising on-chip circuitry through a combination of Joint Test Action Group (JTAG), Universal Asynchronous Receiver/Transmitter (UART), Serial Peripheral Interface (SPI), and other analog interfaces.
Draft and execute scripts to automate tests, extract results, and generate reports using database and investigative tools.

Define architecture and micro-architecture features, write specifications, and understand implementation tradeoffs (e.g., performance, power, frequency, etc.).
Define the CPU block level design document (e.g., interface protocol, block diagrams, transaction level flow, control registers, pipelines, etc.).
Perform RTL development process (e.g., coding and debug in Verilog, SystemVerilog, or VHDL), function/performance simulation debug, and Lint/CDC/FeV/PowerIntent checks.
Contribute to the SoC level integration, and participate in synthesis, timing/power closure, and silicon bring-up.
Participate in test plan and coverage analysis of the block and SoC-level verification.

Plan the verification strategy, identify the platform to validate reasoning components.
Define the test plan along with the strategy with stakeholders along with the sign off exit criteria.
Plan and execute the Verification of Internet Protocols (IPs) using Dynamic Verification and Formal Verification.

Participate in evaluation of future ASIC designs and general architecture for executing Googles data center networking roadmap, off-the-shelf components, vendor co-developments, custom designs, and chiplets.
Collaborate to develop new layer protocols for data center networking.
Understand how everything interacts with software and other ASIC subsystems to implement data center networks.
Define performance hardware/software interfaces. Write micro-architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.

Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs with Strategic Value Add (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs with Strategic Value Add (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

Build and mentor a high-performing team of silicon validation engineers, and foster a culture of collaboration, innovation, and technical excellence.
Develop and execute comprehensive validation plans for Google's custom silicon, covering functional, performance, power, and reliability aspects.
Design and build scalable validation test infrastructure, including hardware setups, software frameworks, and automation tools.
Lead the debug and resolution of silicon issues, collaborate with cross-functional teams such as design, architecture, software, and firmware.
Analyze validation data to identify trends, root causes, and opportunities for improvement in silicon quality and reliability.

Plan the formal verification strategy and create the properties and constraints for digital design blocks.
Utilize formal property verification tools combined with formal verification closure techniques to verify properties.
Resolve difficult to verify properties, and contribute improvements to methodologies to enhance formal verification results.
Architect and implement reusable formal verification components.