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You'll handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You will be the tech lead for CAD within the team, leveraging your extensive backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

Collaborate closely with the ASIC Architecture team to implement an accurate and efficient software model based on the architecture specifications.

Partner with both Software and Hardware design teams, providing support as they use the simulator as the golden reference for hardware implementation.

Ensure the simulator meets the highest standards of performance, reliability, and usability.

Contribute to defining best practices and methodologies for model development, validation, and integration. 

You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You will be leveraging your backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

As the Physical Design Group Leader, you will provide strategic and technical leadership to a team of engineers, guiding them through the entire chip design lifecycle. You will be responsible for the group's output, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab

* Manage and build a world class team managing ASIC design, micro-arch, SDC constraints and integration efforts of the project.
* Translate high level goals to measurable plans and milestones. Lead RTL design, quality checks, and manage schedule for on-time delivery of key IPs.
* Work with verification and physical design teams to achieve high quality design.
* Interface with IP teams and manage schedule and delivery of IPs for successful TO.
* Guide and mentor junior engineers as required.
* Hire and retain tier one engineers and foster teamwork with cross functional collaboration.
* Build a culture of execution excellence coupled with innovation.
* Build a team of hard-working and passionate leaders as we scale.
* Maintain close interactions with NPI, Packaging, DFT, Architecture teams.
* Own power, performance and area optimization of design.

As the leader of the team, you will be responsible for delivering a state-of-the-art functional simulator for the family of routing and switching devices. This simulator is a critical product that streamlines the development process and significantly reduces time-to-market.

In this role, you will:

Lead and mentor and scale the team to 7-10 engineers, fostering a collaborative and inclusive environment
Oversee the design and delivery of a high-performance, reliable, and user-friendly behavioral model for devices
Collaborate closely with cross-functional teams including ASIC Architecture, Software, and Hardware to align goals and ensure seamless execution
Champion engineering excellence by modeling hands-on problem solving and debugging best practices
Guide team members in their professional development with tailored growth plans and regular feedback

Review micro-architecture specifications

Supervise verification team members and provide professional guidance

Implement Verification environment UVM based

Collaborate with Design engineers to resolve bugs and achieve coverage closure

Work with the firmware/Lab teams to verify chip flows

Perform debug, root-cause analysis, and post-silicon validation in the lab

The Design for Test (DFT) team is part of the design group, which focuses on logic design, RTL development, and running verification tests. Their main role is to design test structures embedded within the chip to ensure proper functionality after manufacturing. The goal is to detect potential manufacturing defects with maximum efficiency and filter out faulty units before they reach the market.

The ideal candidate is friendly, social, easygoing, with a good sense of humor, and has the ability to learn independently. They should be located in central\north Israel (Tel-Aviv\Caesarea). Strong independent work skills and job stability are important.



What You'll Do

Work in a small, agile team with an intimate atmosphere that offers direct mentoring and broad professional growth. Insert DFT logic, perform synthesis, and run Automatic Test Pattern Generation (ATPG) to ensure hardware testability. Execute Gate Level Simulations, timing checks, and DRC checks to maintain rigorous design integrity and performance standards. Run regressions and perform deep-dive debugging on simulation failures as part of the core verification process.

physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part in flows development.

we are seeking a networking software engineer to join our rdma transport software team, driving the development of next-generation rdma solutions for ai, cloud, hpc, and Storage. you will research and develop innovative transport algorithms that push the limits of performance and scalability. you will work in a fast-paced, collaborative environment alongside talented engineers from around the world, supporting the data needs of the worlds largest enterprises 
what you'll be doing:
take part in research, design, and development of advanced rdma transport mechanisms and algorithms, enhancing performance, reliability, and scalability.
collaborate closely with hardware engineers, software developers, and system architects to align on project objectives and requirements.
keep up with industry trends and emerging technologies, integrating new ideas and innovations into the development process

we are seeking a highly motivated senior architect for high speed optical systems to join our team of experts and help build the future of high-performance computing. our next-generation infiniband, nvl and ethernet switches will be at the forefront of connecting and powering the world's most advanced compute clusters, from supercomputers used in ai research to high-performance clusters used in vast industries. you will work on some of the most groundbreaking technology as an architect for high-speed optical networks at nvidia. you will help develop next-generation switches and optic engine. the products you'll develop will be coordinated in many groundbreaking compute clusters, and supercomputers, and you'll be part of a team with a strong track record of success.
what you'll be doing:
collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and hardware teams, to ensure the successful execution of the project optimizing rack-to-rack connectivity and fiber routing.
crafting and architecting advanced ultra-fast fiber optic connectivity solutions for nvidia systems.
leading the development and implementation of optic systems to ensure world-class performance and reliability.
analyzing and determining the best approaches for integrating complex optic systems within our infrastructure.
define the optics engine architecture with taking into consideration the system requirement and limitation influencing on the optical engine feature set and technology.
successfully implementing and managing projects to meet ambitious deadlines and performance targets.

we seek a versatile senior software engineer who is passionate about performance optimization and generative ai. our team builds software solutions that enable efficient inference on the latest and greatest generative ai models. we tackle problems on all levels of the stack-from server-level request batching to gpu Kernel fusion-and collaborate with teams across diverse disciplines to push nvidia's hardware to its full potential.
what youll be doing:
cooperate with research teams to onboard new llms and vlms into nvidia's opensource ai runtimes
optimize inference workloads using sophisticated profiling and simulation tools
build solid, extendable inference software systems, and refine robust apis
implement and debug low-level gpu code to harness the latest hw features
own end-to-end inference acceleration features and work with teams around the world to deliver production-grade products

seeking a dynamic and highly motivated senior Software manager to lead our software verification and automation for doca networking sdk. we are looking for a candidate who can excel in a sophisticated, multidisciplinary environment, take ownership, and drive high-quality verification and automation processes. this position offers the opportunity to have a real impact on sophisticated, groundbreaking products, delivered by nvidia and developed by our customers, empowering the most advanced data centers in the world. this role requires close collaboration with teams across various fields (sw, hw, QA ) to elevate our product to the next level.
what you'll be doing:
lead teams of software Verification engineers, providing technical direction, career development, and performance mentorship
define and continuously refine our software testing methodology and processes
engage in a hands-on approach, actively participating in the design, coding, and debugging of verification tests and infrastructure alongside your team
lead the verification process, ensuring the functionality, stability, and performance of our doca networking sdk and the solutions on top of it
work closely with internal and external customers to understand system use cases
analyze coverage measures to identify verification gaps and provide data -driven insights into product development and release readiness