לוח משרות דרושים מהנדס מחשבים בתל אביב יפו

In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.

What you'll be doing:

Lead the end-to-end execution, tracking, and convergence of chip-level CDC and RDC for complex SoCs across all IPs and partitions.

Plan and orchestrate CDC/RDC signoff: define methodology, scopes, run plans, constraints, and acceptance criteria.

Run and maintain CDC/RDC flows and rule decks, including multi-mode, multi-clock, and hierarchical signoff.

Triage violations efficiently: root-cause to RTL, constraints, tool setup, or IP models; prioritize and drive fixes to closure with owners.

Verify reset architecture and RDC robustness (reset domain intent, release sequencing, glitch detection, fanout).

Author and review CDC/RDC constraints, waivers, and justifications; ensure auditability and signoff quality.

Automate runs, report parsing, dashboards, and KPIs for closure tracking using scripting and data tooling.

Partner with RTL, DV, DFT, STA, PD, and Architecture to align fixes, manage ECOs, and protect CDC/RDC quality during late design changes.

Define and enforce signoff gates; communicate progress and risks with clear metrics and issue tracking.

Continually improve methodology and training to prevent recurring CDC/RDC issues and accelerate convergence.

We are looking for a Senior Chip Design Verification Engineer for developing the next generation DFT technologies.

As a Senior Chip Design Verification Engineer in the DFT team, you will verify the design and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and complex products. Our DFT solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.

What you'll be doing:

In this position, you will be responsible for verification of the DFT design, architecture and micro-architecture using sophisticated verification methodologies.

As a member of our DFT verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), execute test/coverage plans, and verify the correctness of the design.

Collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks.

We are at the forefront of AI-driven innovation in VLSI design automation. Join us to shape the future of semiconductor design with cutting-edge AI tools and make a significant impact in a collaborative, high-performance environment. Are you ready to push the boundaries of whats possible in VLSI CAD? Come be part of our pioneering team!

What you'll be doing:
You will be responsible for developing and integrating advanced CAD solutions and automation flows using AI and machine learning for VLSI design, verification, and implementation.
Work closely with design, verification, and CAD teams to identify areas for improving VLSI workflows using advanced tools and methods.
Research, prototype, and deploy AI-based algorithms.
Develop and maintain scripts and automation infrastructure to enable seamless adoption of AI tools in the VLSI design process.
Continuously review emerging AI technologies and methodologies to keep our CAD environment up-to-date.
Provide technical support and training to engineering teams on AI-enabled CAD flows and best practices.

We are looking for an Asic Design Engineer to join the DFT design team and develop the next generation DFT technologies.

As a design engineer in the DFT design team, you will participate in definition and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and sophisticated products, our DFT solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.

What you'll be doing:
In this position, you will be responsible for defining, coding and integrating sophisticated DFT components into various projects and using state-of-the-art technologies.
As a member of our DFT design team, you will participate in defining various DFT features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.
Strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.

We are looking for best-in-class Physical Design CAD Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

You will be in charge of developing physical design, synthesis, STA and Logic eq methodologies for implementation of networking chips and SOCs.

Work closely with block owners. full Chip STA engineers and project managers to assure high quality and timely convergence.

Come up with unique and creative solutions to the state of the art physical design problems that are needed for Our chips.

Additional responsibilities include participating and developing flow and tool methodologies for chip floorplan, power and clock distribution, P&R, timing analysis and closure, power and noise analysis and back-end verification across multiple projects.

We are seeking a System Software Validation Lead to define validation methodologies, set quality standards, and drive a culture of quality across multidisciplinary hardware and software systems. This leadership role emphasizes process ownership, methodology enforcement, and coaching teams, while also providing technical guidance and hands-on validation expertise.
Responsibilities:
Define and enforce validation methodologies, processes, and quality standards across firmware and embedded software.
Lead validation planning and execution reviews, ensuring coverage, consistency, and defect prevention.
Establish automation and CI/CD validation strategies and guide adoption across teams.
Mentor and coach engineers to embed quality practices and foster continuous improvement.
Provide technical leadership in system-level validation, including algorithms and machine learning within firmware and embedded software environments.
Oversee validation execution on ATE platforms, ensuring correlation between simulation, emulation, and silicon test results.
Accountable for high-level analysis of production issues, driving defect escape reviews, enhancing test coverage, and defining quality gates to enforce continuous improvement.

Our Networking System Validation Group is growing, and we are hiring a Junior Switch System Validation Engineer. As a member of the team, you will take part in our core network projects which drive the growth of the company, tech and business wise. You'll gain networking and Switch u-arch knowledge while helping validate, optimize, and debug devices in different areas like Quality-of-Service, performance, logic correctness, and AI features.

You will work closely with logic design, circuit design, and architects to ensure successful product development with aggressive product cycles, in both pre and post silicon stages.

You should have a good grasp of software development in different fields, such as Python Scripting, embedded software, and device firmware. It's important to have experience in a complex emulation environment and show a strong interest in creating, doing, and improving silicon validation plans.

 
What you will be doing:

Work in a combined design and verification team specializing in Switch Full Chip works.

Understand the Switch architecture and build on test plan accordingly.

Develop Full Chip test collaterals/suites, maintain regressions, debug failures and sign-off coverages.

Maintain test suites to facility Emulation and/or Silicon platforms checkout as well.

We are now looking for a Senior verification manager for our FC Switch Silicon team. As a FullChip verification manager in NVIDIA's Networking business unit, you'll lead a group of passionate engineers to design and implement the next generation state-of-the-art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:
Work in a FC team, responsible to integrate and verify the Switch at system level.
Lead and grow a team of FullChip verification engineers.
Responsible to drive the FullChip verification execution, including staging plan of the projects and deliveries.
Provide technical guidance, mentoring, and support to engineers in the team.
Work closely with multiple teams within organizations such as Architecture, u-arch, Full chip Micro-Architecture, BE, and FW.
Dynamic verification environments planning for units infrastructures and system level.
Work with design/verification team which develops core units within the Switch silicon.

In this role, you'll guide a team of experienced engineers and team leads, coordinating execution across multiple product lines. You'll have a direct impact on our networking products-from VR72 to next-generation AI fabric solutions-and play a key role in scaling our capabilities while pioneering AI-enhanced workflows.

What you'll be doing:

Guide day-to-day execution across multiple concurrent product lines, with ownership of firmware debug and validation delivery.

Mentor and develop team leads (currently 3 direct reports), helping them grow their technical and leadership capabilities while thoughtfully allocating resources across priorities.

Collaborate with teams across Chip Design, Software, Architecture, QA, and Applications to solve technical challenges together.

Encourage AI adoption and explore AI-enhanced workflows that improve team effectiveness.

Help translate customer needs into meaningful product improvements.

We are looking for a passionate and experienced software developer to join our Chip Design Technologies group, helping to build the software infrastructure and tools that shape the future of Chip Design and Verification. This role works at the intersection of infrastructure engineering, tooling, and database ownership. Youll be responsible for the backbone systems that enable the development of our industry-leading networking chips - the highway for the AI revolution.

We're looking for a senior hands-on engineer who combines deep expertise in Python automation and SQL data flows with a passion for large-scale compute environments. If youre excited about optimizing critical systems, owning the health of compute farms, and driving reliability across cross-functional teams, youll feel right at home here.

What youll be doing:

Partner with Chip Design teams to solve engineering bottlenecks: Collaborate closely with Design, Verification, and Methodology teams to identify workflow pain points and deliver infrastructure solutions that directly improve chip design productivity and quality.

Build automation infrastructure: Design, build, and maintain robust Python-based automation infrastructure that orchestrates chip design flows, monitoring, and infrastructure tooling.

Drive data integrity and performance: Own the MySQL/SQL schemas, migrations, and data integrity for our infrastructure tools. You will optimize queries and indexes to ensure our databases scale with our massive growth.

Own the platform health: Take ownership of the day-to-day health, capacity, and reliability of our compute farm and storage systems. This includes leading incident response, triage, and implementing long-term fixes to ensure high availability.

We are looking for an excellent Firmware Design Engineer for our FW PHY Group. The person will closely work with our FW development, architecture, chip design teams and gain deep understanding of our Networking products and technologies. We have some of the most forward-thinking and hardworking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best chip design team in the industry!

What youll be doing:

Work on the next development Fusion GPU project.

Design and develop PHY-layer firmware for cutting-edge networking devices.

Enabling new SerDes and physical linkup flows.

Work closely with the architecture, HW, and SW design teams.

Define implement and maintain FW algorithm to control the Silicon.

Develop and test FW on emulation & simulation environments during the Pre-silicon phase.

Debug and screen HW/FW/SW issues.

Take an active part in silicon bring-up and SW development phases.

Lead data-driven discussions about the product functionality and areas for improvement.

We are looking for best-in-class Physical Design Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you will be doing:

Physical design of blocks/top-level according to specifications under challenging constraints targeting for the best power, area, and performance.

Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.

Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.

Taking part inflows development.

Act as Partition/Unit level physical design technical leader and focal point.

As a Senior Software Engineer in the GPU Networking Architecture team, youll lead advanced development and POC efforts for AI infrastructure solutions. You'll be collaborating with experts across distributed AI, deep learning, networking OS, virtualization, storage, and more. Come and join us for the cutting edge in GPU Networking!

What youll be doing:
Drive advanced development and POCs for AI infrastructure solutions in cutting-edge AI networks, integrating innovative software and hardware.
Demonstrate team architectural concepts with larger NVIDIA AI software stacks.
Work closely with various groups within NVIDIA to bring AI network technologies to reality, including GPU and Switch HW and SW teams, Product as well as fellow architects.

As a Senior Software Architect in the Accelerated Computing System and Software team, you will define Software Defined Networking (SDN) architectural solutions and be part of a team of specialists who span across numerous technological fields related to the modern data center, such as distributed AI and deep learning systems, High Performance Computing (HPC), Networking Operating Systems, Virtualization, Storage, and more.

What youll be doing:

Define system and software architecture for Software Defined Networking (SDN) of ground breaking emerging AI and HPC networks which involves innovative software and hardware.

Be an active member in setting the use-cases and metrics for Monitoring Complex High-speed Networks Control-plane.

Work closely with various groups within NVIDIA to bring AI and HPC network technologies to reality, including GPU and Switch HW and SW teams, Product as well as fellow architects.

We seek a highly motivated and experienced System Architect specializing in Data-Center, AI Fabric, and Ethernet Networking to join our team of experts and help shape the future of high-performance ML/AI computing. You will have the opportunity to work on some of the most pioneering technologies and help drive the innovation of our next-generation networks. You will play a key role in defining end-to-end solutions, networking protocols and features, interworking with orchestration systems, and help address new business opportunities in exciting areas. Our Architects also represent us in open-source projects, technical conferences, and standard development organizations.

What you'll be doing:

Explore new technologies and end-to-end solutions for our Ethernet Networking Platforms.

Be familiar with data-center and AI fabric network topologies, AI/ML clusters operation and network usage, as well as with the Ethernet Switch platforms' design and characteristics.

Define robust architectures and technical requirements for network operating systems and end-to-end solution offering for AI/ML workloads' needs and highly performing network operations.

Lead the work with R&D and Validation teams, providing technical guidelines and close support and thorough reviews for detailed designs and test plans.

Collaboration with architects across various fields, including Chip Design, Firmware, Hardware Platforms, and System teams.

Close work with product marketing, program managers, and account managers to ensure the successful execution of projects.

Support engagements with key customers, issue patents, publish white papers and blogs, and be proactive in technical forums and industry working groups.

Promote innovation through the design and implementation of Proof-of-Concept (PoC).