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Were looking for an experienced SW Team Manager to join our Simulators Team, where you'll lead the design and development of our hardware simulators - functional and performance models that serve as the source of truth, drive architectural exploration and compiler optimization.
Our simulators model diverse cores within a cutting-edge SoC designed to accelerate Big Data and Database Analytics.
You will collaborate closely with hardware and software teams, contributing to co-design efforts that influence architecture, tooling, and system-level behaviour.
Responsibilities:
Lead & grow a team of experienced engineers
Develop new hardware simulators and continue evolving existing one.
Collaborate with Architecture, VLSI, and Software teams to drive co-design initiatives.
Provide insights that influence chip architecture, compiler optimization, and system-level performance.
Develop tools that drive the chip development cycle.

we are seeking a highly technical, partner-facing Integration Engineer to join our Network team. In this role, you will be the primary technical driver for onboarding partners to the Network and maintaining quality and product excellence with existing partners.
You arent just following a manual; you are a technical consultant, a troubleshooter, and a bridge builder. You will work closely with R&D, Product, and Business, ensuring that every provider integration is seamless, secure, and scalable.
What Youll Do:
Own the Integration Lifecycle: Lead partners from initial discovery through to production go-live, serving as their dedicated technical Point of Contact.
Act as Tier 1 R&D: Deep-dive into the code to answer complex architectural questions. Youll debug, write code, analyze API logs, and solve technical hurdles.
Bridge the Gap: Translate business needs into technical requirements. Youll help partners understand how to map their existing infrastructure to our protocol.
Collaborate Cross-Functionally: Work hand-in-hand with Product to relay feedback from the field and with Business to ensure the providers commercial goals are met.
Scale the Process: Develop technical documentation, tools, and integration best practices to streamline the onboarding process and making it more intuitive.

As a Senior AI Engineer on the Guardian Agents team, you will develop both our autonomous "digital employees" that execute security programs and the Control Plane that governs them. You will build a platform that allows customers to calibrate agents through conversation, ensuring human feedback is transformed into persistent organizational knowledge. By engineering these closed-loop systems, you enable agents to learn, evolve, and deliver accurate, goal-driven security outcomes at scale.
What Youll Do:
Architect Autonomous Agents: Build goal-driven agents for complex security tasks like false-positive reduction and automated triage.
Build the Control Plane: Develop the infrastructure for Human-in-the-Loop (HITL) feedback, natural language calibration, and stateful memory systems.
Engineer for Growth: Implement evaluation frameworks and "organizational memory" to ensure agents stay accurate and follow historical security precedents.
Bridge AI & Engineering: Collaborate in a "Core Pod" with Security Researchers and Data Scientists to turn raw security signals into scalable, productized agent behaviors.
Scale Data Pipelines: Integrate agents with Big Data foundation to ensure real-time context and tenant-safe execution.

In this role, you can lead our teams to deliver fully functional "first silicon" IP designs, from defining initial constraints through high-quality tape-out. You will have the rare and rewarding privilege of crafting upcoming products that will delight and inspire millions of customers every single day.
Responsibilities
Own the entire IP-level netlist generation and timing convergence journey, from synthesis and UPF power intent to final sign-off.
Architect and manage complex timing constraints (SDC) for both standard and custom designs, ensuring sign-off quality from day one.
Drive Full Chip and block-level timing/noise convergence, including hierarchical timing flows and power optimizations.
Collaborate closely with RTL designers to understand clock architecture, DFT teams on mode constraints, and PNR teams to achieve flawless physical convergence.
Develop and support automated block and chip-level sign-off flows, working with CAD teams to shape cutting-edge methodologies that eliminate pessimism and accelerate convergence.
Perform deep-dive signal integrity (SI) and noise analysis, drive custom IP integration, and generate block-level budgets to ensure correlation with the Full Chip.

This is a highly visible role where you will own the physical design cycle at the partition, IP, and Chip levels-enabling us to produce fully functional "first silicon" designs. Do you love working on challenges that no one has solved yet? If you are ready to join the world's leading engineers and work with state-of-the-art design flows, come join our group.
Responsibilities
You will be responsible for all phases of pre-silicon development, from initial definition to high-quality tape-out (Netlist to GDSII).
Lead block-level Place & Route (PnR), complex floor-planning, partitioning, and the creation of power domains and grid specifications.
Develop and validate high-performance, low-power clock network guidelines and distribution.
Drive static timing closure (STA), Physical Verification (DRC/LVS), and Electrical/Power analysis (EM, IR-Drop, Xtalk, and Noise).
Participate in establishing CAD and physical design methodologies for "correct-by-construction" designs and assist in flow development for chip integration.
Generate and implement ECOs to fix timing, noise, and EM/IR violations while meeting strict area and power constraints.
Work closely with logic design teams on SoC architecture and HDL (Verilog) to implement timing fixes and design optimizations.

Appdome’s mission is to protect every mobile app in the world and the people who use mobile apps in their lives and at work.
Appdome provides mobile brands with the only patented, centralized, data-driven Mobile Cyber Defense Automation platform, delivering rapid no-code, no-SDK mobile app security, anti-fraud, anti-malware, anti-cheat, anti-bot implementations, configuration as code ease, Threat-Events™ threat-aware UI/UX control, ThreatScope™ Mobile XDR, and Certified Secure™ DevSecOps Certification in one integrated system.
With Appdome, mobile developers, cyber and fraud teams can accelerate delivery, guarantee compliance, and leverage automation to build, test, release, and monitor the full range of cyber, anti-fraud, and other defenses needed in mobile apps from inside mobile DevOps and CI/CD pipeline.
Leading financial, healthcare, m-commerce, consumer, and B2B brands use Appdome to upgrade mobile DevSecOps and protect Android & iOS apps, mobile customers, and mobile businesses globally. Today, Appdome's customers use their platform to secure over 50,000+ mobile apps with protection of over 1B mobile end users projected. About The Position We are looking for a talented Mobile Fraud Engine to join Appdome. In this role, you will develop sophisticated fraud detection and prevention components that operate at the core of our mobile threat intelligence platform — diving into signal processing, risk evaluation logic, and real-time decision-making, and translating your findings into robust, production-ready code. This position is ideal for developers who want to understand how fraud happens and use that knowledge to build innovative solutions that protect millions of mobile applications worldwide. Job Description
* Design, develop, and maintain core fraud detection and risk-scoring components within mobile apps.
* Investigate fraud patterns and mobile threat signals to develop innovative detection and prevention mechanisms.
* Own the collection of threat and device signals used by risk assessment algorithms to perform device and user behavioral profiling.
* Design systems that make split-second decisions, balancing security accuracy with user experience.
* Continuously explore emerging fraud trends and incorporate new detection techniques into our product.
* Collaborate with a multidisciplinary team of engineers, data scientists, and security experts to deliver end-to-end solutions.

Design, implement, and test a state-of-the-art optimizing compiler for Cisco Silicon One
Evaluate and optimize code performance, including debugging, code generation improvements, and pipeline analysis
Develop, optimize, and enhance the compiler backend to fully leverage cutting-edge hardware capabilities
Solve complex resource management challenges across hardware pipelines
Design and implement new P4 language features that empower network application developers
Build and maintain the compiler toolchain for custom networking applications
Contribute to libraries, analysis tools, and supporting infrastructure
Collaborate with cross-functional hardware and software teams
Work closely with ASIC engineers on next-generation IC design, influencing hardware through compiler insights prior to tape-out

We push the boundaries of technology, developing innovative DFT solutions that drive industry-leading programmability, scalability, and performance. Our team operates in a hybrid model, with three days a week in the office in Midtown Tel Aviv or Caesarea, fostering collaboration and technical excellence in a startup-like atmosphere within a stable, global corporation.

Your Impact

As an Experienced DFT Engineer, you will:

Own and drive DFT execution across the full product lifecycle, from pre-silicon design through post-silicon debug and production qualification.

Define and align DFT architecture and strategy in close collaboration with chip architects, design, and verification teams.

Oversee and contribute hands-on to the implementation of DFT features, including ATPG, scan insertion and compression, and memory BIST.

Lead silicon debug activities and root-cause analysis, driving corrective actions to improve yield, reliability, and test quality.

Establish, standardize, and evolve DFT methodologies and best practices across projects.

Develop PHY firmware and system-level features for advanced networking ASICs
Participate in post-silicon validation, including lab bring-up, debugging, and performance analysis
Collaborate closely with PHY, system, firmware, and silicon design teams
Contribute to defining system operation modes and end-to-end device behavior
Help drive the development of next-generation, high-scale networking solutions using cutting-edge silicon technologies

We are seeking an experienced technical leader to head our collective communication library development team. This role involves leading a team of engineers in developing high-performance collective communication implementations for multi-NPU and multi-node AI workloads.
Key Responsibilities
Lead the design and development of collective communication primitives (All-Reduce, All-to-All, Gather/Scatter and etc)
Architect scalable communication protocols for multi-NPU and multi-node systems
Optimize communication performance for NPU architectures
Provide technical leadership to the team members in NPU programming, distributed systems, and communication protocols
Work with a success-driven worldwide international team (Network, NPU, QA, AI, DL/ML Framework)
Define project milestones, deliverables, and technical roadmaps
Ensure compatibility with major AI frameworks (PyTorch, TensorFlow, JAX).

own the responsibility for delivering networking features and their verification aspects.
define, develop and maintain verification infrastructure and regression tests suites - make TEST suites robust, maintainable and easy portable.
work with continuous integration system, regression tools, automate builds, run TEST suites and analyzing results.
innovate!

physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part in flows development.

seeking a dynamic and highly motivated senior Software manager to lead our software verification and automation for doca networking sdk. we are looking for a candidate who can excel in a sophisticated, multidisciplinary environment, take ownership, and drive high-quality verification and automation processes. this position offers the opportunity to have a real impact on sophisticated, groundbreaking products, delivered by nvidia and developed by our customers, empowering the most advanced data centers in the world. this role requires close collaboration with teams across various fields (sw, hw, QA ) to elevate our product to the next level.
what you'll be doing:
lead teams of software Verification engineers, providing technical direction, career development, and performance mentorship
define and continuously refine our software testing methodology and processes
engage in a hands-on approach, actively participating in the design, coding, and debugging of verification tests and infrastructure alongside your team
lead the verification process, ensuring the functionality, stability, and performance of our doca networking sdk and the solutions on top of it
work closely with internal and external customers to understand system use cases
analyze coverage measures to identify verification gaps and provide data -driven insights into product development and release readiness

looking for a motivated ai-native software engineer to join us in shaping the future of software development. engineers on this team grow fast - they work alongside senior architects, use cutting-edge ai tools daily, and become the organization's first experts in ai-native development practices.
as a ai-native software engineer in the ai-native development team, you will be Embedded in development teams adopting ai-assisted workflows. you will use the tools daily, identify friction points, suggest improvements, and become the team's go-to expert for ai-native development. this is a learning-intensive role with high impact - you will directly shape how the organization builds software with ai.
what you'll be doing:
use ai-assisted development tools daily as part of a team building real projects.
identify and report friction points - articulate clearly what works, what doesn't, and why.
contribute to tool improvements based on hands-on experience.
help document best practices, playbooks, and usage guides for broader rollout.
experiment with new ai tools, models, and approaches - evaluate and share findings with the team.
support development teams by providing direct feedback on tools and process during poc development.

we are seeking a senior customer program manager - ai datacenter to support the planning and execution of technical and operational programs for key partners and maintain strong customer relationships. as a key member of the customer program management team, this role will drive collaboration with major enterprise customers, cloud service providers, tier-1 partners, and oems. the ideal candidate will bring strong technical program management expertise, a solid engineering background, and the ability to thrive in fast-paced environments while ensuring successful outcomes for both internal teams and external collaborators.
what youll be doing:
define and manage program schedules, deliverables, and turning points aligned with customers and partners roadmaps and requirements.
translate customer requirements into actionable tasks for all functional teams, driving timely issue resolution across engineering, quality, logistics, and sales.
provide horizontal leadership to drive cross-functional program execution, managing high priority issues/concerns, and coordinating globally dispersed teams to ensure clear alignment on objectives.
act as the primary customer interface, facilitating program kick-offs, technical discussions, design reviews, issues/bug tracking and resolution, customer qualification/validation efforts, and status updates throughout the product lifecycle.
drive program execution from design through production deployment, ensuring on-time delivery, quality, and customer acceptance.
provide ongoing post-deployment sustaining support, serving as case manager for field quality issues or high priority concerns with major enterprise customers, cloud service providers
monitor factory production schedules, yields, and blockers, collaborating with odm/contract manufacturers to resolve issues and meet operational targets with major enterprise customers, cloud service providers
proactively communicate program health, risks, and key issues to both customers, internal partners, and leadership (hardware, software, operations, business, quality, sales, and product teams), ensuring transparency and alignment.