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Required Field Application Engineer - AI Accelerators
In this position:
You will serve as the primary technical interface between us and our customers for our AI accelerator product line and future accelerator platforms. You will support customers through the full product lifecycle - from pre-sale technical engagement and proof-of-concept development through production deployment and ongoing field support. You will work hand-in-hand with R&D to investigate and resolve complex issues, develop reference applications and demos, and act as a trusted technical advisor to both customers and internal teams.
Responsibilities
Develop a comprehensive understanding of each customers use case, system architecture, and integration requirements, serving as their primary technical point of contact for all accelerator-related topics.
Provide deep technical support across the accelerator portfolio, including the Dataflow Compiler, model compilation, and runtime integration.
Reproduce, investigate, and drive resolution of complex hardware and software issues in close collaboration with R&D, spanning PCIe integration, driver-level debugging, inference pipeline optimization, and power management.
Lead technical alignment with customers - clearly communicating issue status, setting expectations, coordinating across internal teams, and ensuring customer satisfaction.
Design and implement customer-facing demo and reference applications in C/C++, showcasing accelerator capabilities at major industry events such as CES and other trade shows.
Support pre-sale technical activities including solution scoping, feasibility assessments, and technical presentations to prospective customers.
Provide knowledge transfer and technical enablement to FAEs and partners to scale field support effectiveness.
Collaborate closely with R&D, Product, and Business teams to translate customer needs into actionable product requirements and roadmap input.

we are looking for forward-thinking, self-motivated engineers who thrive in fast-paced environments and "crisis times." Beyond technical excellence, successful candidates are:
Intrinsically, see the importance of every detail in "elegant solutions."
Excellent interpersonal and communication skills to work across diverse functional areas.
Schedule-driven with a desire to solve challenges that have never been solved before.
Responsibilities
Micro-Architecture & RTL: Design and implement high-quality, power-efficient RTL (Verilog/SystemVerilog) from block-level to sub-system levels.
Cross-Functional Collaboration: Partner with Architecture, Algorithm, Software, and Physical Design (PD) teams to translate product requirements into GDS-ready silicon.
Front-End Flow Management: Take ownership of "correct-by-construction" design tasks, including Synthesis, Lint, CDC/RDC (Clock/Reset Domain Crossing), and STA (Static Timing Analysis).
Verification Support: Work closely with Design Verification (DV) and Formal Verification teams to define coverage requirements, develop testbenches, and debug functional/performance issues.
Post-Silicon & Validation: Support pre-silicon emulation (FPGA, Palladium) and post-silicon validation in lab environments to ensure spec compliance.

In this role, you can lead our teams to deliver fully functional "first silicon" IP designs, from defining initial constraints through high-quality tape-out. You will have the rare and rewarding privilege of crafting upcoming products that will delight and inspire millions of customers every single day.
Responsibilities
Own the entire IP-level netlist generation and timing convergence journey, from synthesis and UPF power intent to final sign-off.
Architect and manage complex timing constraints (SDC) for both standard and custom designs, ensuring sign-off quality from day one.
Drive Full Chip and block-level timing/noise convergence, including hierarchical timing flows and power optimizations.
Collaborate closely with RTL designers to understand clock architecture, DFT teams on mode constraints, and PNR teams to achieve flawless physical convergence.
Develop and support automated block and chip-level sign-off flows, working with CAD teams to shape cutting-edge methodologies that eliminate pessimism and accelerate convergence.
Perform deep-dive signal integrity (SI) and noise analysis, drive custom IP integration, and generate block-level budgets to ensure correlation with the Full Chip.

As a Design Verification Engineer, you will be responsible for ensuring "bug-free first silicon" for complex IP and SoC designs. You will drive all phases of pre-silicon verification, from defining methodologies and test plans to RTL freeze and tape-out sign-off. These roles are highly collaborative, requiring close interaction with architecture, design, and software teams across global sites.
Responsibilities
Architect and develop scalable, portable verification environments, including UVM-based testbenches, protocol monitors, agents, and checkers.
Define detailed test and coverage plans based on micro-architecture specifications and extract features for DV attributes.
Create and simulate test scenarios, perform advanced debugging, and conduct end-to-end simulations of data/control paths.
Drive regression and coverage analysis (metric-driven verification) to ensure the highest quality, productivity, and time-to-market.
Partner with architects and designers from the early stages of feature definition to influence IP/SoC specifications.
Apply formal verification, hardware acceleration, and power/performance (NLP) analysis where applicable.

we are looking for a Senior Design Engineer who wants to push boundaries, work hard, and help build something that has never been done before.

The Senior Design Engineer will join a team responsible for the architecture, design, and verification of a high-performance controller ASIC at the core of this new computational paradigm.

Your Day to Day
Own the design, micro-architecture, and implementation of digital logic for a high-performance ASIC
Translate system-level requirements into detailed micro-architecture and RTL designs
Develop high-quality RTL code in Verilog/SystemVerilog
Work closely with the algorithm, verification, analog, and software teams to define interfaces and ensure end-to-end functionality
Participate in design reviews, propose improvements, and ensure compliance with coding and design guidelines
Integrate and debug digital modules in simulation and lab environments
Support synthesis, timing closure, performance optimization, and power reduction activities
Collaborate with verification teams to define test plans and ensure thorough coverage
Contribute to a high-intensity startup environment where solving tough technical challenges and meeting ambitious schedules is part of the mission

Space Systems Development Manager We are seeking an experienced Space Systems Development Manager to lead the development of advanced space systems from concept through delivery.
Responsibilities:
Lead multidisciplinary teams across systems, software, and hardware
Manage end-to-end development, including requirements, design, integration, and validation
Drive system architecture and ensure successful delivery.

We are currently seeking a Senior FPGA Engineer to join one of our trading teams. While our company has been leveraging FPGA technology for a number of years, you will have the opportunity to build an FPGA application from scratch for an existing team. Were seeking a candidate that has a strong understanding of software and hardware interaction. This person will participate in the full development lifecycle, including system and block level testing, of low latency high throughput FPGA design.
Responsibilities:
Architect and implement new FPGA applications (synthesis, place & route, static timing analysis, documentation) from the ground up
Research and evaluate a variety of cutting-edge FPGA hardware and technologies
Propose creative solutions to overcome FPGA/hardware limitations
Liaise directly with software and other design teams
Conduct lab debugging and characterization of new hardware.

We are seeking a Technical Project Manager with proven expertise in High-Speed Board Design and hardware project management to join our Firewall Core Group.
Job Id: 22794
This role involves leading complex, cross-functional projects that combine hardware and software, driving innovation for our Security Gateways.
Key Responsibilities
Lead hardware/software projects from planning through delivery.
Manage board design, hardware development, and prototype builds (EVT, DVT, PVT) with contract manufacturers.
Coordinate across R&D, QA, PMO, and Product Management teams.
Oversee software release processes and infrastructure changes.
Maintain schedules, mitigate risks, and manage external vendors.

At Lumissil, we are driving innovation in automotive technology, developing solutions that power the next generation of vehicles. We are looking for a Junior Engineer who is eager to learn, grow, and make an impact in a dynamic and innovative environment. This is a unique opportunity to work alongside experienced professionals, gain hands-on experience, and contribute to projects at the forefront of automotive electronics. If you are passionate about technology, curious to explore new challenges, and excited to make a real difference, Lumissil is the place to develop your skills, innovate, and grow your career. Why join us?
* Work on cutting-edge automotive projects
* Learn from a talented and supportive team
* Gain exposure to real-world automotive challenges
* Grow your career in a collaborative and inspiring environment If you’re ready to take the next step in your career and be part of something meaningful, we’d love to meet you! About The Position: As a Junior ASIC Design Engineer at Lumissil, you will take part in the full lifecycle of advanced chips that power the next generation of vehicles. This is a hands-on, growth-oriented role where you’ll work closely with experienced ASIC engineers, gain exposure to real silicon, and build a strong foundation in chip design and verification. In this role, you will:
* Be part of a professional ASIC team working on cutting-edge automotive solutions
* Support and learn from real emulation platforms used in production-grade designs
* Contribute to RTL implementation and gain practical experience in design flows
* Assist with verification and backend (BE) activities, learning industry best practices
* Participate in silicon bring-up, seeing your work come to life on real hardware This position is ideal for curious engineers who want to learn fast, take ownership, and grow into a key contributor in the world of automotive semiconductor design.

We push the boundaries of technology, developing innovative DFT solutions that drive industry-leading programmability, scalability, and performance. Our team operates in a hybrid model, with three days a week in the office in Midtown Tel Aviv or Caesarea, fostering collaboration and technical excellence in a startup-like atmosphere within a stable, global corporation.

Your Impact

As an Experienced DFT Engineer, you will:

Own and drive DFT execution across the full product lifecycle, from pre-silicon design through post-silicon debug and production qualification.

Define and align DFT architecture and strategy in close collaboration with chip architects, design, and verification teams.

Oversee and contribute hands-on to the implementation of DFT features, including ATPG, scan insertion and compression, and memory BIST.

Lead silicon debug activities and root-cause analysis, driving corrective actions to improve yield, reliability, and test quality.

Establish, standardize, and evolve DFT methodologies and best practices across projects.

As a key member of the team, you will be responsible for developing a state-of-the-art functional simulator for the family of devices. This simulator is a critical product that streamlines the development process and significantly reduces time-to-market.

In this role, you will:
Design, implement, and validate components of the behavioral model for SiliconOne devices
Collaborate with ASIC Architecture, Software, and Hardware teams to ensure alignment and seamless integration
Apply engineering best practices for code quality, performance, testing, and documentation
Troubleshoot and resolve complex technical issues
Contribute to defining best practices and methodologies for model development, validation, and integration

Develop PHY firmware and system-level features for advanced networking ASICs
Participate in post-silicon validation, including lab bring-up, debugging, and performance analysis
Collaborate closely with PHY, system, firmware, and silicon design teams
Contribute to defining system operation modes and end-to-end device behavior
Help drive the development of next-generation, high-scale networking solutions using cutting-edge silicon technologies

You'll handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You will be the tech lead for CAD within the team, leveraging your extensive backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

Collaborate closely with the ASIC Architecture team to implement an accurate and efficient software model based on the architecture specifications.

Partner with both Software and Hardware design teams, providing support as they use the simulator as the golden reference for hardware implementation.

Ensure the simulator meets the highest standards of performance, reliability, and usability.

Contribute to defining best practices and methodologies for model development, validation, and integration.