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We are looking for a Senior Algorithm engineer to join a high-velocity R&D team developing advanced Real-Time algorithms for mission-critical defense systems. The role focuses on designing, implementing, and evolving estimation, inference, and decision algorithms that operate under real-world constraints such as uncertainty, latency, partial observability, and adversarial conditions. You will take ownership of core algorithmic components from theoretical formulation through deployment in operational systems.
Responsibilities:
Design, implement, and maintain Real-Time estimation and inference algorithms operating on heterogeneous sensor inputs. Develop and tune probabilistic state-estimation models, including non-linear filters, adaptive models, and prediction mechanisms. Implement uncertainty management, gating, clustering, hypothesis handling, and state lifecycle logic. Integrate AI/ML components where they provide measurable value (classification, anomaly detection, decision support). Own algorithm performance across stability, convergence, latency, and numerical robustness metrics. Translate operational and system -level needs into mathematical formulations and deployable algorithms. Collaborate closely with system engineers and software teams to integrate algorithms into Real-Time command-and-control environments. Analyze operational data, simulations, and edge cases; iteratively refine models based on empirical performance. Participate in algorithm design reviews, trade-off analyses, and performance assessments.

Fire-Arc is an innovative, data-oriented, high-tech company that owns, develops, and publishes multi-platform digital Assets. All our products and content coordinate together to create unique monetization solutions and advanced revenue streams for digital properties. We are expanding our teams and are focused on adding like-minded, result-oriented, and high-achieving talents. We are looking for a Junior QA Engineer to join one of our Scrum teams and support the quality of our web and desktop applications. The primary focus of this role is executing regression tests, testing new features, and contributing to web test automation using Playwright. Impact and Responsibilities
* Execute manual regression tests to ensure product stability across releases.
* Test new features and bug fixes, validating functionality against requirements and expected behavior.
* Design, write, and maintain clear and structured test cases and test scenarios.
* Analyze test results, identify defects, and provide detailed and reproducible bug reports.
* Perform ongoing manual test coverage for areas that are not yet automated.
* Run and maintain existing Playwright-based automated tests for web applications.
* Run and analyze API tests using tools such as Postman, validating responses, data, and error handling.
* Perform data validation to ensure data accuracy, consistency, and integrity across systems and application layers.
* Test features that rely on cloud-based services, validating integrations, configurations, and expected system behavior.
* Collaborate with developers and product managers to understand features, clarify requirements, and improve test coverage.
* As part of the Scrum team, support the quality ownership of the team’s deliverables.

Advantages:

* Basic knowledge of JavaScript or TypeScript.
* Experience running automated tests in CI/CD pipelines.


Brand:
FireArc

You will be responsible for:
* Systems Administration of the core systems and tools related to customer journey
* Configure databases, automations and UI/UX.
* Ensure data integrity, user management, and governance across the stack.
* Build and maintain cross-system integrations using iPaaS solutions to ensure seamless data flow between tools.
* Being a main stakeholder in the AI builders group to integrate wisely cutting edge technologies together with the well-stabled primitive systems.
* Partner with the cross-business operations team, mainly with RevOps, DevOps and FinanceOps teams.
* Identify manual processes and design scalable automation solutions.
* Support dashboards, KPIs, and analytics initiatives with well-structured data pipelines.
* Support new tool evaluations, and implementation projects.
* Provide training, documentation, and best-practice enablement for end-users.


About Alice:
Alice is a trust, safety, and security company built for the AI era. We safeguard the communicative technologies people use to create, collaborate, and interact—whether with each other or with machines. In a world where AI has fundamentally changed the nature of risk, Alice provides end-to-end coverage across the entire AI lifecycle. We support frontier model labs, enterprises, and UGC platforms with a comprehensive suite of solutions: from model hardening evaluations and pre-deployment red-teaming to runtime guardrails and ongoing drift detection.

Hybrid:
Yes

Our Chip Design team is growing! Join our high-end product design team and help shape the next generation of advanced semiconductor solutions. About us our company  has been delivering tens of millions of chips annually to leading tier-1 customers in the Security, Cloud, and Computing domains. We specialize in semi-custom, high-quality solutions, going above and beyond to meet our customers needs. Our Israel Design Center is fully self-contained, covering everything from product definition and architecture to design, software, validation, and TEST - meaning real ownership and no daily late-night calls across time zones We also pride ourselves on a warm, open culture where everyone knows each other, and every engineer can clearly see the impact of their work on the final silicon. We are looking for experienced Chip Design Engineers to join our team and take a key role in RTL design, new IP development, and SOC integration As part of the design team, you will be deeply involved in architectural exploration, protocol evaluation, and hands-on design work across multiple chip blocks. Responsibilities
* RTL design and implementation of new IPs
*  SOC integration and design ownership of chip subsystems
* Exploration and evaluation of new protocols and architectural solutions
* Close collaboration with architecture, verification, validation, software, and back-end teams
* Delivering high-quality, best-in-class RTL that meets performance, power, and area goals Why Join Us?
* Work on cutting-edge, high-volume silicon products
* Real impact on end-to-end chip development
* Collaborative environment with strong technical ownership
* A stable yet agile organization with a human, people-first culture

We are looking for best-in-class Physical Design Power Engineer to join our outstanding Networking Silicon Power engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput, lowest latency and best Power! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you will be doing:

Power Optimization of Physical design, of blocks/top-level/fc under challenging constraints.

Optimization involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise fixes.

Power estimation and power modeling.

We are now looking for a Senior Chip Design Engineer to join our Switch Silicon team. As a Chip Design Engineer in our Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state-of-the-art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What You'll Be Doing:
Work in a design/verification team which develops core units within the Switch silicon.
Micro-architecture of rtl verification environments planning for units and modules.
Design RTL of units/blocks according to Arch. specifications under challenging constraints with high orientation to power, area, and performance.
RTL synthesis, timing, supporting verification, and silicon post TO activities.
Work closely with multiple teams within organizations such as Architecture, u-arch, Full chip Micro-Architecture, BE, and FW.

We are now looking for a Senior Chip Design Verification Engineer to join our Switch Silicon team.As a Chip Design Engineer at NVIDIA's Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state-of-the-art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What You'll Be Doing:
Work in a design/verification team which develops core units within the Switch silicon.
Micro-architecture of dynamic verification environments planning for units and modules.
Design dynamic verification environments of units/blocks according to Arch. specifications under challenging constraints with high orientation to power, area, and performance.
Work closely with multiple teams within organizations such as Architecture, u-arch, Full chip Micro-Architecture, BE, and FW.

We are looking for a Power U-arch Senior Engineer. NVIDIA is known as a world leader in providing energy-efficient high-performance products and we continue to invest in the research and development of hyper-efficient SOC architectures. We are continually innovating in creative and unrivaled ways to improve our ability to deliver exceptional Perf/Watt solutions in a wide range of sectors and verticals. Come join NVIDIAs Applied Power team to develop state of the art DPU products.

What you'll be doing:
Lead a micro-architecture of power features such as: Power management, Logical Power features, etc
Work with DPU Arch team on power features definition.
Understand the workload characteristics for DPU workloads at System Scale to drive new HW/SW features for Perf@Watt improvements.