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As a PNR/PD-CAD team member, you will have an impact on a wide range of activities and domains in the PD world. The team develops and supports utilities that enable an efficient work environment for the physical design teams across the world.

The role includes exploring new technologies and methodologies of first-of-its-kind designs, and the complex implementation of designs from small ones to the largest possible.
The job includes hands-on work and impact on all aspects of the design cycle, from infrastructure-related automation for design efficiency through developing internal PNR flows, which will enable improved designs - from PNR implementation through developing infra, signoff flows & verification utilities.

Responsibilities:
The job includes constant work with different teams and disciplines that interface with the PNR world, which includes Timing, power delivery, synthesis, Physical Verification, and more.
Along with the different disciplines, you will work with different teams, from vendors, PD team members and other CAD team members and discipline owners across the world to enable and improve the productivity of the PD flows.

You will join a dynamic quality assurance engineering team, responsible for functional and performance validation of Wi-Fi (and other wireless technologies) features on Apple products. In this role you will be responsible for design and development of automation for testing embedded firmware and entire systems. You will be required to lead investigations and analyze failures or performance behavior. It is required to master the skills of problem solving, creativity and programming along with achieving detailed understanding of embedded systems and our wireless protocols.

In your role as a senior PHY Algorithms Development Engineer, as part of Apple Connectivity Group, you will be part of a world-class group that pioneers design and development of Physical Layer algorithms for wireless communication systems for Apple products. We live in a mobile and device driven world where knowledge of the physical world around us is needed. We rely on this knowledge to get around, to learn about our environment and to enable spectacular new features for custom applications. Apple is meeting those needs as robustly and as creatively as possible and is interested in people who want to help meet that commitment. The success we are targeting will be the result of very skilled people working in an environment which cultivates creativity, partnership, and thinking of old problem in new ways. If that sounds like the kind of environment that you find intriguing, then let's talk.

We are looking for a candidate who can innovate and integrate signal processing technologies for solving novel and diverse sets of problems in various wireless communication and sensing technologies:
- Develop communication signal processing algorithms for best-in-class implementation of various wireless standards.
- Conduct basic research of existing solutions in literature.
- Involvement in block level spec definition.
- Perform mathematical analyses of the given problem and its proposed solutions.
- Implement floating-point simulations to prove spec compliance of suggested solutions.
- Implement fixed-point modeling and simulation to allow performance sign-off and RTL bit-exact development.
- Write detailed design documents that will enable implementation of algorithms by other teams specializing in either RTL design or DSP firmware coding.
- Optimize and fine-tune the system for spec compliance on silicon in an RF lab environment.

This role is for an analog layout IP lead who will enable us to produce fully functional first silicon IP designs. The responsibilities include all phases of silicon development from definition to high quality production.

Senior Layout Leads are responsible for delivering Analog Mixed-Signal IP in an SOC flow. They collaborate with teams of highly skilled individuals to develop the next generation of world-leading SOCs.
As a member of the AMS layout team you will be responsible to deliver Physical Design Verification clean layout, this includes the following:
Crafting complex layout for mixed signal, and analog circuits in deep SubMicron CMOS technologies.
Reviewing and analyzing floor-plans and complex circuits with circuit designers.
Running complete set of design verification tools available on AMS blocks.
Working with the circuit design team to plan/schedule work and negotiate any necessary layout trade-offs as needed.
Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout.
Exceeding engineering specifications and expectations by working closely with the circuit design team.
Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area and power requirements.

We are seeking a highly skilled and experienced Project Manager to oversee and drive the successful execution of strategic deliveries.
The ideal candidate will have a proven track record of managing multiple projects, coordinating cross-functional teams, and ensuring alignment with business objectives.
This role requires excellent leadership, problem-solving, and communication skills to deliver results in a fast-paced environment.
you will:
Manage project/s scope, content control, schedule, and budget
Maintain direct contact with customers and build long-term relationships
Manage risks and mitigation plans
Lead the overall project plan in a global environment across company divisions: R&D, QA, Operations, Integration, and Support.
Define, prioritize, negotiate, and communicate customer requirements
Manage third-party suppliers
Escort the pre-sales process for new sales opportunities, including estimated timelines and efforts
Play an active role in the technical analysis and resolution of issues

In this role you will be responsible to model, analysis and estimate power consumption of daily use cases on our next generation SoCs. Drive new ideas into micro-architecture, design and circuits to reduce SoC power across the dynamic range. Drive budgeting, measurement and analysis of overall SoC power for many use cases of interest. You Will work extensively with many teams across every stage of the project from Architectural definition through Design implementation and SW management to focus on power optimization.
To be successful in this role, you must have keen interest and motivativation to deliver best experience to our users, and wide perspective in order to work simultaneously on multiple disciplines. This role is required working closely with many cross-functional teams and good understanding of hardware and software interaction at system level.

In this highly visible role, you will be responsible for SOC power simulation and power modeling, SOC use case power analysis, and drive the future SOC power optimization.