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We are seeking an Embedded team leader to join our team in North We are looking for an experienced Embedded software development team leader who will serve as a professional leader, Support Engineers, and drive professional involvement in projects, while also managing new employee onboarding. Key Responsibilities:
* Managing and onboarding new employees
* Providing professional support to engineers
* Professional involvement in projects

As a member of our ML group, you will research and build AI systems that change how our silicon is designed. Many of these problems are still open: the right way to frame the problem isn't known yet, and the data is scarce or noisy.

We are looking for a strong researcher who enjoys working closely with design teams to turn open-ended questions into well-posed research problems, and who wants to see the results used in real projects. Success in this role means models and agents that measurably improve designed chip metrics (Power, Performance, and Area) and design turnaround. You will join a growing team of AI and software engineers working with our chip design teams.

Responsibilities
Research and develop AI methods for the physical design flow, from floorplanning and placement through routing and timing closure, combining predictive models, optimization, and generative AI.
Design and build agentic workflows that connect LLMs to EDA tools, design data, and internal infrastructure, to automate and speed up tasks such as flow setup, debug, design exploration, and analysis.
Work with design teams to turn open-ended problems into well-defined research questions with clear metrics, baselines, and success criteria.
Develop robust AI methods for limited, noisy, or imbalanced data, leveraging domain knowledge and advanced learning techniques.
Own data end to end: extract useful signal from EDA tool outputs and design databases, validate and clean it, and build datasets and benchmarks where none exist.
Run careful experiments and evaluations for both models and agents, and report clearly what works and what doesn't.
Work with software engineers and design teams to bring promising prototypes into production flows, and improve them based on feedback from real projects.
Help shape new research directions as our work grows, follow the AI and EDA literature, and bring relevant ideas to the team.

We are looking for talented engineers to join our STA team. In this role, you will be working closely with multiple integration teams, like DFT, Top Level PNR, PHY designers and PNR teams.


You will be responsible for:
Develop/support automated block and full chip level signoff flows.
Full Chip Timing/Noise convergence and full signoff for high quality TO
Enable hierarchical Timing flows.
Power optimizations.
Generate block level budget and context for correlation with Full Chip.
Drive custom IP integration and custom timing checks flows.
Close work with Design, DFT, architecture and Power team.

As a manager in the RTL/FE CAD team, you have the opportunity to shape the future of chip design and impact our engineers who develop the next generation of our products! You will lead a high-impact team that develops software solutions used by thousands of RTL design and integration engineers globally across all chip families (iPhone, iPad, Mac, Apple Watch, and more).
In this role, you will be a key catalyst in transforming front-end hardware design into a modern, agile discipline. You will spearhead the transition to agentic workflows-redefining how RTL and integration teams operate in the AI era. This role combines deep knowledge of RTL/FE flows with modern software engineering practices, people leadership, and a transformative vision for engineering methodology.

Responsibilities
People Leadership: Lead, mentor, and grow a team of ~20 CAD engineers, driving talent acquisition, technical mentorship, performance management, and career development.
Agentic Flow & Methodology Transformation: Drive the team and broader RTL/FE community toward agentic workflows. Act as an organizational change agent, pioneering modern, agile methodologies that transform daily design and integration practices.
LLM Harness & Agentic Tooling: Own the architecture and execution of the LLM harness for RTL/FE flows (e.g., autonomous violation triage for Lint/CDC/RDC, intelligent connectivity synthesis, and design assist agents). Establish rigorous benchmarks to continually evaluate and elevate workflow accuracy and autonomy.
RTL Integration & Connectivity Tooling: Own end-to-end RTL integration tools, including connectivity generation, SoC assembly automation, IP packaging, and structural checks.
Static Sign-off Checks: Drive methodology, deployment, waiver governance, and sign-off metrics for Lint, CDC, RDC, and related static verification domains.
Roadmap & Milestone Alignment: Define strategic roadmaps and near-term execution plans aligned with multi-project tapeout milestones and long-term organizational goals.
Stakeholder & EDA Vendor Partnership: Collaborate closely with RTL design and integration leads to turn evolving design challenges into robust software solutions. Partner with EDA vendors to resolve escalations and influence tool roadmaps.
Software Excellence: Champion software engineering best practices, modern Python development, scalable cloud architectures, and robust CI/CD infrastructure within CAD.