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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
in this role, you will help build socs by driving quality and reliability processes from the integrated circuit (ic) perspective. working with various cross-functional teams, you will develop quality and reliability specifications, develop and deploy design guidelines, and develop and execute TEST plans. within the larger organization, you will collaborate with global hardware quality and reliability, silicon design, validation, and engineering teams. you will have an understanding of ic flows, wafer processing, testing, qualification, yield, reliability, and failure analysis.the ml, systems, & cloud ai (msca) organization at google designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all google services (search, youtube, etc.) and google cloud. our end users are googlers, cloud customers and the billions of people who use google services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including google clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
define and lead qualification hardware and TEST developments in front of internal teams and external vendors.
define and execute silicon and package qualification activities (e.g., htol, elfr, esd/lu, b/hast, thb, etc.).
extract, manipulate, and analyze large volumes of data from silicon and package qualification programs (e.g., htol, elfr, esd, lu, uhast, tct, etc.), high volume mfg, and field returns to identify failure mechanisms, reliability trends, and opportunities for yield, quality, and reliability improvement.
own cross-functional investigation of ic quality and reliability issues to identify root causes and develop solutions (e.g., rma triage, analytics, failure analysis, etc.).
develop and implement physics-based statistical quality and reliability models (e.g., elf, tddb, nbti, hci, time zero failures, etc.) to predict silicon device failure mechanisms, degradation patterns, and lifetime behaviors.
Requirements:
minimum qualifications:
bachelor's degree in electrical engineering, materials science, a related technical field, or equivalent practical experience.
2 years of experience in ic silicon quality or reliability.
experience in semiconductor cmos technology, device physics, failure mechanisms, and accelerated TEST methodologies.
experience in reliability modeling, data analytics, and statistics.
preferred qualifications:
experience in semiconductor reliability, manufacturing processes (e.g., fab, assembly, TEST ), or ic and packaging failure mechanisms and related failure analysis.
experience in data analytics, especially to identify commonalities and abnormalities.
knowledge of design-for-reliability guidelines and implementation techniques.
familiarity with TEST methods and hardware for silicon qualification (e.g., htol chambers, esd, lu, etc.).
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
as part of our server chip design team, you will use the asic design experience to be part of a team that creates the SOC vlsi design cycle from start to finish. you will collaborate with design and Verification engineers in active projects, creating architecture definitions with rtl coding, and running block level simulations.the ml, systems, & cloud ai (msca) organization  designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all google services (search, youtube, etc.) and google cloud. our end users are googlers, cloud customers and the billions of people who use google services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including google clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
lead the design activities at ips, subsystems(s.s) and SOC.
plan, execute, track progress, assure quality, report status of the assigned activity.
lead a team of designers both directly and in teams.
define the block/ SOC level design documents such as micro architectural specifications.
own ip, s, SOC strategies for clocks, resets, and debugs. enforce global methodologies and drive enhancements.
Requirements:
minimum qualifications:
bachelor's degree in electrical engineering, computer engineering, Computer Science, a related field, or equivalent practical experience.
8 years of experience in rtl design cycle from ip to SOC and from specification to production.
8 years of experience in technical leadership.
experience in the following areas: rtl design, design quality checks, physical design aspects of rtl coding, and power.
preferred qualifications:
experience with synthesis techniques to improve register-transfer level (rtl) code, performance and power as well as low-power design techniques.
experience with design for TEST and its impact on design and physical design.
experience with a scripting language like Python or PERL.
knowledge in one of these areas: pcie, ucie, ddr, axi, chi, fabrics, and arm processors.
knowledge of SOC architecture and assertion-based formal verification.
knowledge of high performance and low power design techniques.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
25/03/2026
Location: Haifa
Job Type: Full Time
FPGA Verification engineer (6160) We are seeking a talented and experienced FPGA Verification engineer to join our hardware development team. In this role, you will be responsible for defining and executing comprehensive verification strategies for complex FPGA-based systems, from architectural definition through system integration.
Requirements:
FPGA Verification engineer (6160) We are seeking a talented and experienced FPGA Verification engineer to join our hardware development team. In this role, you will be responsible for defining and executing comprehensive verification strategies for complex FPGA-based systems, from architectural definition through system integration. You will work closely with FPGA designers, system architects, algorithm teams, and board designers to ensure high-quality and robust designs using advanced verification methodologies and tools. Key Responsibilities Develop and maintain advanced verification environments using SystemVerilog and UVM
Write testbenches, behavioral models, monitors, and scoreboards
Create directed and constrained-random TEST scenarios
Execute simulations, analyze results, and perform in-depth debugging
Define and track functional and code coverage metrics
Collaborate with design engineers to identify and resolve design issues
Support system integration and bring-up activities
Contribute to verification planning and documentation Required Qualifications B.Sc. in Electrical Engineering, Computer Engineering, Computer Science, or related field
5+ years of experience in FPGA/ASIC verification
Strong proficiency in SystemVerilog
Hands-on experience with UVM methodology
Experience with simulation tools such as ModelSim, Questa, VCS, or equivalent
Solid understanding of digital design and FPGA architectures
Strong debugging and problem-solving skills Location: Haifa, Israel
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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