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דרושים ביערה פיינר-אבחון והשמה
מיקום המשרה: חיפה וקרית ביאליק
סוג משרה: משרה מלאה
לחברה טכנולוגית העוסקת בפיתוח מערכות אוויריות לשוק הביטחוני והאזרחי,
דרוש/ה מהנדס/ת אלקטרוניקה מנוסה

תפקיד פיתוח חומרה מקצה לקצה.
עבודה במטה החברה באזור חיפה והקריות

תיאור התפקיד
אחריות מלאה על פיתוח חומרה, משלב הקונספט והתכנון ועד לייצור סדרתי.
תכנון סכמות למעגלים אנלוגיים ודיגיטליים, ספקי כוח מסוג LDO וDC/DC וממשקים אלקטרוניים.
תכנון ועריכת כרטיסים אלקטרוניים (PCB Layout), כולל Placement, Routing, Stack-up ודרישות DFM.
בחירת רכיבים אלקטרוניים על בסיס Datasheets, זמינות, מחזור חיי מוצר ושיקולי אמינות.
ביצוע Bring-up, בדיקות חומרה ואיתור תקלות (Debug) במעבדה.
הכנת תיעוד הנדסי, לרבות BOM, ICD ומסמכי ECO/ECN.
השתתפות בסקרי תכן (Design Reviews).
עבודה בצוות פיתוח רבתחומי בשיתוף מהנדסי מכניקה ותוכנה.
דרישות:
תואר ראשון בהנדסת חשמל או אלקטרוניקה - חובה.
ניסיון של 5 שנים לפחות בתכנון כרטיסים אלקטרוניים - חובה.
ניסיון מוכח בפיתוח כרטיסים מקצה לקצה, כולל Schematics, PCB Layout וBring-up - חובה.
ניסיון בתכנון מעגלים אנלוגיים ודיגיטליים, ספקי כוח וממשקים - חובה.
ניסיון מעשי בPCB Layout, לרבות Stack-up וDFM - חובה.
שליטה מלאה בתוכנת Altium Designer - חובה.
ניסיון בבחירת רכיבים לפי Datasheets, Derating, Lifecycle וAvailability - חובה.
ניסיון בביצוע Debug ובדיקות חומרה באמצעות Oscilloscope, DMM, ספקי כוח וLogic Analyzer - חובה.
ניסיון בהכנת תיעוד הנדסי מסוג BOM, ICD וECO/ECN - חובה.
יכולת הובלה עצמאית של פרויקט חומרה משלב Concept ועד ייצור סדרתי - חובה.
אנגלית טכנית ברמה גבוהה - חובה.

ניסיון בתכנון כרטיסים למערכות מוטסות, רחפנים או כטב"מים, תוך התייחסות לEMC, משקל ותנאי סביבה - יתרון משמעותי.
ניסיון בתכנון כרטיסים מבוססי מיקרובקרים STM32 או TI - יתרון.
ניסיון בתכנון מעגלי RF או מעגלים להנעת המשרה מיועדת לנשים ולגברים כאחד.
 
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משרה בלעדית
2 ימים
מיקום המשרה: מספר מקומות
תנאים נוספים: מספר סוגים
להקמה ותפעול תחנת כוח בין-לאומית דרוש /ה מנהל /ת תפעול תחנות כוח מנוסה משרה 87565
במסגרת התפקיד: ניהול תפעול שוטף של תחנת הכוח לייצור חשמל.
בקרת איכות ושמירה על תקני בטיחות, אחריות על לוחות זמנים ועמידה בתקציב, טיפול בבעיות ניהול שוטפות של התחנה
משרה מלאה
תנאי שכר מעולים + רכב!
דרישות:
מהנדס/ת חשמל/מכונות -רצוי תואר ראשון
ניסיון של לפחות 3 שנים בהקמה או ניהול תחנת כוח - חובה
ניסיון בעבודה מול קבלנים ויכולת ניהול צוותים.
שליטה מלאה בתוכנות Office ו-AutoCAD.
יכולת ניתוח והבנה של תוכניות טכניות.
נכונות לעבודת שטח בתנאי עבודה מאתגרים המשרה מיועדת לנשים ולגברים כאחד.
 
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משרה בלעדית
2 ימים
דרושים באי.אס טופ פרוג'קטס בע"מ
מיקום המשרה: מספר מקומות
סוג משרה: משרה מלאה
לאי. אס טופ פרוגקטס דרוש /ה מפקח /ת חשמל למפעל בטחוני גדול בצפון
פיקוח והובלת פרויקטי הקמה של מבני ציבור ותעשייה בתחום החשמל, מערכות חשמל ותשתיות.
הפעלת קבלנים בשטח ופיקוח טיב, איכות ובטיחות.
קריאה ועדכון של תכניות בנייה ושרטוטי חשמל.
מתן מענה מקצועי הנדסי לבעיות שעולות מהשטח ועוד.
רכב ותנאים מעולים למתאימים!
דרישות:
הנדסאי/ת או מהנדס/ת חשמל מדופלם/ת - חובה!
ניסיון של למעלה מ-5 שנים בתפקיד דומה - חובה!
ידע וניסיון בפיקוח על קבלנים בשטח, חלוקה משימות ותיאום בין עבודות בשטח.
ידע וניסיון בעבודות חשמל ותשתיות בפרויקטי הקמה של מבנים תעשייתיים וציבוריים.
שליטה מלאה בקריאת תכניות בנייה ושרטוטי חשמל. המשרה מיועדת לנשים ולגברים כאחד.
 
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
3 ימים
דרושים באלביט מערכות
מיקום המשרה: חיפה
סוג משרה: משרה מלאה
אנחנו מחפשים
לאתר החברה בחיפה דרוש.ה מהנדס.ת מערכת לפיתוח מערכות ראש מתקדמות לטייסים.
בוא.י לקחת חלק בפיתוח מערכות חדשניות ומשמעותיות המשולבות במערכי הקרב המתקדמים ביותר. בתפקיד זה תוביל.י פיתוח ואינטגרציה של מערכות מולטי-דיסציפלינריות מתקדמות, תעבוד.י עם טכנולוגיות פורצות דרך ותשפיע.י על פתרונות מבצעיים עבור טייסים ולוחמים. אם את.ה מחפש.ת עשייה טכנולוגית מאתגרת בסביבה חדשנית, עם ממשקים רחבים והשפעה מערכתית אמיתית - מקומך איתנו.

במסגרת התפקיד
הובלת פיתוח, אינטגרציה והטמעה של מערכות ראש חדשניות לטייסים ולמערך הקרקעי
הגדרת דרישות מערכת וביצוע ניתוחים הנדסיים
תכנון ארכיטקטורה מערכתית והתאמת פתרונות טכנולוגיים
ניהול אינטגרציה ובדיקות מערכת מקצה לקצה
ליווי תהליך העברה לייצור והטמעה מבצעית
עבודה מול צוותי פיתוח, לקוחות וספקים בארץ ובחו"ל
ניהול טכני של פרויקטים מורכבים ועבודה מול ממשקים מרובים
דרישות:
תואר ראשון בהנדסת אווירונאוטיקה / חשמל / תוכנה
תואר שני בהנדסת מערכת - יתרון
ניסיון כמהנדס.ת מערכת או בפיתוח מערכות מולטי-דיסציפלינריות - יתרון
ניסיון בבדיקות מערכת, העברה לייצור והטמעה - יתרון
ניסיון בעבודה עם מערכות מוטסות או מערכות צבאיות - יתרון
ניסיון בהובלת צוותים טכניים - יתרון
אנגלית ברמה גבוהה
יכולת למידה עצמאית, חשיבה מערכתית, עבודה בצוות, הנעת עובדים ויכולת ניהול מספר משימות במקביל

*רק פניות מתאימות יענו המשרה מיועדת לנשים ולגברים כאחד.
 
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Design Verification SoC Lead, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work to shape the future of an edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive cutting-edge distributed inference technology that powers real-time systems where latency and reliability are mission-critical.
You will be part of a team that pushes boundaries, developing robust, autonomous solutions that define the next generation of intelligent infrastructure and hardware for the edge. You will contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy complex AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Lead a team of chip verification engineers. Plan tasks, allocate people, hold verification design/code reviews, and drive verification execution.
Plan the verification of digital design blocks, including writing test plans, and other verification documents.
Work closely with Architecture, Software, Design, and Physical Design stakeholders to make technical decisions and represent project status throughout the development process.
Develop verification features and capabilities, and participate in RTL debug.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
10 years of experience working with hardware verification languages (e.g., System Verilog/Specman), design verification methodologies (e.g., Universal Verification Methodology (UVM)) and chip design flow.
Experience in leading chip verification teams through the full lifecycle from concept to delivery.
Experience in creating chip or subsystem design verification strategies and plans.
Preferred qualifications:
15 years of experience in verification of complex SoC/ASIC.
10 years of experience managing verification teams.
Experience in chip design/verification of high performance AI/ML accelerators.
Experience with industry verification techniques, including complementary techniques such as formal verification, and emulation.
Experience in low power verification.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior Silicon DFT Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will play a crucial role in Design for Testing (DFT) Architecture and DFT design, and support devices of extreme complexity to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality matrix throughout the project life-cycle, and providing sign-off DFT to tapeout.The ML, Systems, & Cloud AI (MSCA) organization designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all services (Search, YouTube, etc.) and Cloud.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead and execute activities in the design, implementation, and verification of DFT solutions for large-scale ASICs.
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage the DFT team's workload and deliverables, provide technical leadership and guidance to the team.
Lead DFT execution of a silicon project (e.g., planning, execution, tracking, quality, and signoff).
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
8 years of experience in Automatic Test Pattern Generation (ATPG) methods.
Experience with multiple projects in DFT design and verification, DFT specification, definition, architecture, and insertion.
Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow.
Experience in leading DFT activities throughout an ASIC development flow.
Preferred qualifications:
Master's degree in Electrical Engineering or a related field.
Experience in JTAG and iJTAG protocols and architectures.
Experience in post-silicon test or product engineering.
Experience in SoC cycles, silicon bring-up, and silicon debug activities.
Knowledge of fault modeling techniques.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
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8843805
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required SoC Chip Architect, Cloud, Silicon
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As an SoC Chip Architect, you will lead the definition of groundbreaking, high-performance custom silicon and multi-chiplet systems for our Cloud AI infrastructure. You will bridge the gap between hyperscale data center workload requirements and silicon implementation across various domains, collaborating with cross-functional partners to design scalable, energy-efficient, and feature-rich SoCs.
You will be part of a team pushing the boundaries of custom silicon engineering, architecting next-generation data center products that deliver industry-leading performance, low latency, and massive bandwidth for Cloud and our flagship AI services.
Responsibilities
Lead top-level SoC architecture across multiple disciplines, including IP architects, digital design, verification, physical design, validation, firmware, power management, security, and system software.
Architect and analyze complex multi-chiplet systems, including chip partitioning, die-to-die (D2D) interconnects, advanced packaging constraints, and high-performance on-chip fabrics (NoC).
Define top-level SoC subsystems, memory hierarchies, clock distribution, reset schemes, and power domains to ensure optimal system performance and operational efficiency.
Formulate end-to-end operational flows, latency models, and system throughput analyses for data center workloads.
Own the SoC architecture specification and lead it throughout the complete product life-cycle: concept, modeling, implementation, tape-out, and post-silicon bring-up.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
15 years of experience leading the architectural definition of high-performance SoCs, ASICs, or multi-chiplet systems from concept through production.
Experience architecting SoC interconnects, memory hierarchies, and system-level fabrics.
Experience writing, owning and maintaining comprehensive SoC architecture specifications.
Experience working across hardware, firmware, and system software boundaries with system-level reasoning.
Preferred qualifications:
Masters degree or PhD in Electrical Engineering or Computer Engineering.
Experience with AI workload analysis, their mapping across different data center system components, and optimizing hardware solutions to better serve them.
Experience scaling and optimizing high-performance AI accelerators, compute chiplets, or IO Hub SoCs for data center/cloud deployments.
Proven track record of architecting multi-chiplet systems utilizing cutting-edge silicon process technology and advanced packaging (2.5D/3D, D2D interfaces such as UCIe, BoW, or high-speed SerDes).
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Micro-Architect, Networking, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
Lead Design Activities at IPs, SubSystems(S.S) and SoC.
Define the block-level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power, and FPGA/silicon bring-up, as well as test plan development and coverage analysis for block and SOC-level verification.
Communicate and collaborate with multi-disciplined and multi-site teams.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related technical field, or equivalent practical experience.
8 years of experience architecting networking ASICs from specification to production or equivalent experience.
4 years of experience in technical leadership.
Experience developing RTL for ASIC subsystems.
Experience in micro-architecture, design, verification, logic synthesis, and timing closure.
Experience in micro-architecture, RTL Design, verification, design quality checks, physical design aspects of RTL coding, and power.

Preferred qualifications:
Experience architecting networking switches, end points, and hardware offloads.
Experience working with design networking: RDMA or packet processing and system design principles for low latency, high throughput, security, and reliability.
Experience working with software teams optimizing the hardware/software interface.
Proficiency in a procedural programming language (e.g., C++, Python, Go).
Knowledge of TCP, IP, Ethernet, PCIE and DRAM.
Familiarity with Network on Chip (NoC) principles and protocols (AXI, ACE, and CHI).
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
8843779
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v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Silicon Test and DFT Engineer, Cloud
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Responsibilities
Collaborate with Architecture, Design and Verification teams to develop new product bring-up, validation, characterization, and qualification strategies and manufacturing test solutions for new High Performance Computing (HPC) products in advanced process technologies.
Verify test solutions on pre-silicon models (simulation or emulation) and develop Automated Test Equipment (ATE) test modules and binning flows.
Develop and validate test programs on Automated Test Equipment (ATE) platforms for new product integration (NPI) in preparation for high-volume manufacturing (HVM), working with ATE vendors and internal cross-functional teams.
Manage product sustainment support, including analyzing volume data, improving test time and yield, assessing test escapees and return merchandise authorizations (RMAs), localizing failures, implementing containment measures, and partnering with design, manufacturing, and quality and reliability teams to identify root causes and implement corrective actions.
Build tools, flows and methodologies to continuously improve and automate the testing life-cycle.
Requirements:
Minimum qualifications:
Bachelor's degree in Engineering, Computer Science, a related field, or equivalent practical experience.
10 years of experience in test engineering.
Experience in pre-silicon validation, test content generation, automatic test equipment (ATE) program development, and post-silicon enabling from new product introduction (NPI) through high-volume manufacturing.
Experience with ASIC test methodologies (MBIST, ATPG, DFT, SerDes, and sensors).
Experience with Python, Java, C# or C/C++ and Advantest or Teradyne ATE platforms.
Preferred qualifications:
Masters in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
10 years of experience in test engineering, including product engineering.
Experience with CPU/GPU SoC architecture, design, validation and debug.
Experience in advanced testing methodologies and data analysis, including system to tester correlation, yield and test time analysis and improvement, etc.
Demonstrated expertise in developing automations for pre-silicon verification and post-silicon test-generation/test-program domains.
Inquisitive and motivated to venture into, and improve, all aspects of post-silicon testing from definition to realization.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8843764
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v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Requred SoC Power Architect, Cloud, Silicon
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Power Architect, you will not just design chips; you will define the energy efficiency of the infrastructure that powers our services worldwide.
In this role, you will be at the intersection of architecture, logic design, physical implementation, and system software. You will own the power architecture for next-generation custom SoCs (System on Chips), making critical trade-offs between performance, thermal constraints, and power delivery to build the most efficient computing platforms on the planet.
Responsibilities
Define and own the SoC power architecture, including complex power domains, clocking structures, and power delivery network (PDN) solutions to achieve optimal performance-per-watt.
Architect sophisticated power management policies, including dynamic voltage and frequency scaling (DVFS), power gating, and state strategies. Define the hardware/software interface for the Power management unit (PMU) and provide power management specifications.
Lead collaboration across architecture, RTL, physical design, packaging and validation teams to establish power budgets and specifications. Ensure power requirements are met from concept to tape-out.
Develop high-fidelity power and performance models to evaluate architectural features early in the design cycle. Drive pre-silicon power estimation and analysis to guide design decisions.
Lead post-silicon power analysis, correlating lab measurements with pre-silicon models to close the loop and improve future methodologies.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
10 years of experience in ASIC/SoC architecture or design with a focus on power optimizations.
Experience developing or using power and performance modeling tools to drive architectural trade-offs.
Experience in low-power design techniques (e.g., UPF/CPF, multi-voltage islands, power gating, clock gating, etc.) and on-chip power management IP.
Preferred qualifications:
Masters degree or PhD in Electrical Engineering, Computer Engineering, or a related field.
Experience in the design and analysis of full-chip power integrity, including interactions between clocking, reset, and power sequencing.
Experience with post-silicon bring-up, power calibration, thermal management, and debugging in a lab environment.
Experience with data center or server SoC power architecture and management requirements.
Experience with industry-standard EDA power tools (e.g., Conformal LP, Power-Artist, PrimeTime-PX, Joules) and simulation environments.
Familiarity with modern workload analysis (AI/ML, transcoding, networking) and their impact on SoC power profiles.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8843762
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דיווח על תוכן לא הולם או מפלה
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v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Staff Signal Integrity Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Lead end-to-end signal integrity definition, channel budgeting, and stackup optimization for complex multi-die packages, including 2.5D (CoWoS, EMIB, InFO), 3D vertical stacking, and high-density organic substrates.
Architect and optimize multi-terabit interconnects across Die-to-Die (UCIe/BoW), host links (PCIe Gen6/7, PAM4/# SerDes), and memory subsystems (HBM3/4, DDR5, LPDDR6) in close collaboration with PHY and silicon design teams.
Build high-accuracy 3D full-wave electromagnetic models (HFSS) for micro-bumps, C4 bumps, TSVs, interposers, and BGA transitions, establishing automated flows for statistical eye/BER margin analysis.
Define high-frequency test vehicles, fixtures, and measurement methodologies; execute multi-port VNA, TDR, and real-time scope characterizations to correlate lab measurements with predictive simulations.
Collaborate closely with Silicon Design, Package Layout, Board/System, and external foundry/OSAT partners to resolve design trade-offs
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
10 years of experience in Signal Integrity (SI), Power Integrity (PI), or high-speed hardware packaging.
Experience in electrical channel modeling, jitter budgeting, and return loss/crosstalk optimization for high-speed serial or parallel interfaces (e.g., PCIe Gen5/6, SerDes PAM4, DDR5, or Die-to-Die interconnects).
Experience with lab measurement equipment, including multi-port Vector Network Analyzers (VNA), Time-Domain Reflectometry (TDR), and high-bandwidth real-time oscilloscopes for simulation correlation.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience leading SI/PI technical architecture for server-class CPUs, high-performance AI accelerators (TPUs/GPUs), or multi-chiplet modules (MCM).
Experience developing automated EM extraction, layout parsing, and high-throughput statistical eye/BER margin analysis pipelines using Python, MATLAB, or Tcl.
Ability to lead cross-functional technical teams, mentor engineers, and drive technical roadmaps with external OSATs, substrate manufacturers, and foundries.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8843755
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v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior SOC and IP Design Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with digital reasoning design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog.
Experience with reasoning synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power and design techniques.
Experience in reasoning design and debug with Design Verification (DV).
Preferred qualifications:
Experience with a scripting language like Python or Perl.
Experience with design sign-off and quality tools (e.g., Lint, clock domain crossing (CDC), etc.).
Knowledge of System on a chip (SOC) architecture and assertion-based formal verification.
Knowledge of design techniques.
Knowledge in one of these areas: Peripheral Component Interconnect Express (PCIe), Universal Chiplet Interconnect Express (UCIe), Double Data Rate SDRAM (DDR), Advanced Extensible Interface (AXI), ARM processors.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8843747
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סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior SoC Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
8 years of experience with creating and using verification components and environments in standard verification methodology.
Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, or a related field.
3 years of experience with creating and using verification components and environments in standard verification methodology.
Experience with verification techniques, and the full verification life cycle.
Experience with performance verification of ASICs and ASIC components.
Experience with Application-Specific Integrated Circuit (ASIC) standard interfaces and memory system architecture.
Experience in four or more System on a chip (SOC) cycles.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8843742
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דיווח על תוכן לא הולם או מפלה
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שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required CPU Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, and system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning and test execution to collecting and closing coverage.
We're the driving force behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing,
Responsibilities:
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and universal verification methodology (UVM), or formally verify designs with SystemVerilog assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
4 years of experience with creating and using verification components and environments in standard verification methodology.
Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, or a related field.
3 years of experience creating and using verification components and environments in standard verification methodology.
Experience with Application-Specific Integrated Circuit (ASIC) standard interfaces and memory system architecture.
Experience with verification techniques, and the full verification life cycle.
Experience with performance verification of ASICs and ASIC components.
Knowledge of CPU/Processor architectures (e.g., pipeline, cache, memory subsystem, instruction sets, exceptions) like ARM, X86 or RISC-V, for verifying processor cores or IP blocks.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8843740
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סגור
דיווח על תוכן לא הולם או מפלה
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v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior SoC Test Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
Collaborate with Architecture, Design and Verification teams to develop new product bring-up, validation, characterization, and qualification strategies and manufacturing test solutions for new High Performance Computing (HPC) products in advanced process technologies.
Verify test solutions on pre-silicon models (simulation or emulation) and develop ATE test modules and binning flows.
Develop and validate test programs on Automated Test Equipment (ATE) platforms for new product integration (NPI) in preparation for high volume manufacturing (HVM), working with ATE vendors and internal cross-functional teams.
Product sustain support, including volume data analysis, test time and yield improvements, assess test escapees and RMAs, localize failures, implement containment measures and partner with design, manufacturing, quality and reliability teams to root cause and implement corrective actions.
Develop tools, flows and methodologies to continuously improve and automate the testing life cycle.
Requirements:
Minimum qualifications:
Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or related
8 years of experience in test engineering
Experience in pre-silicon validation, test content generation, ATE program development, and post-silicon enabling from new product introduction through high volume manufacturing.
Experience with ASIC test methodologies (e.g., mbist, atpg, dft serdes, sensors).
Experience in Python, Java, C# or C/C++ and Advantest or Teradyne ATE platforms.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
10 years of experience in test engineering, including product engineering.
Experience with CPU/GPU SoC architecture, design, validation and debug.
Experienced in advanced testing methodologies and data analysis, including system to tester correlation, yield and test time analysis and improvement, etc.
Demonstrated expertise in developing automations for pre-silicon verification and post-silicon test-generation/test-program domains.
Ability to be motivated to venture into, and improve, all aspects of post-silicon testing from definition to realization.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8843732
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סגור
דיווח על תוכן לא הולם או מפלה
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סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior SoC Product Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
Develop and implement strategies for high volume manufacturing of SoC products, including troubleshooting, ATE test coverage optimization, DPPM reduction, test cost reduction, power and performance assurance, and product data integration and correlation between system, ATE, and SLT.
Drive interactions with wafer fab and OSATs, own and drive checkpoints for key quality metrics.
Drive volume ramp and mass production through test program releases, volume data analytics, lot disposition, extended test time reduction, yield improvement, and RMA handling.
Support setup and maintenance of test, diagnosis, and yield analysis infrastructure, including Return Merchandise Authorization (RMA) support.
Collaborate with cross functional teams across the globe including ATE and SLT Test Engineering, Quality and Reliability (Q&R), Packaging, Supplier Management and Operations to build, deploy, and maintain a high volume manufacturing screening solution.
Requirements:
Minimum qualifications:
Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
8 years of experience in product engineering or test engineering.
Experience developing on Advantest 93K or Teradyne UltraFlex ATE platforms.
Experience with product engineering, supply chain data analytics, or diagnostics for High Volume Manufacturing (HVM) or NPI.
Preferred qualifications:
Experience with industry standards, design tools, and DFT best practices, including at-speed TDF, ATPG, MBIST, memory repair, diagnostic tools, and yield improvement.
Experience evaluating customer returns with ATE and SLT, identifying coverage gaps, developing incremental structural and functional patterns to address quality issues.
Experience delivering HVM screening solutions for high performance computing chips in advanced technology nodes with low Defective Parts Per Million (DPPM).
Knowledge of statistical analysis (e.g. JMP), Yield Management Systems (e.g. Exensio, YieldExplorer, JMP), or Python for data analytics.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8843334
סגור
שירות זה פתוח ללקוחות VIP בלבד
סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required SoC Test Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
Collaborate with Architecture, Design and Verification teams to develop new product bring-up, validation, characterization, and qualification strategies and manufacturing test solutions for new High Performance Computing (HPC) products in advanced process technologies.
Verify test solutions on pre-silicon models (simulation or emulation) and develop ATE test modules and binning flows.
Develop and validate test programs on Automated Test Equipment (ATE) platforms for new product integration (NPI) in preparation for high volume manufacturing (HVM), working with ATE vendors and internal cross-functional teams.
Product sustain support, including volume data analysis, test time and yield improvements, assess test escapees and Return Merchandise Authorization (RMAs), localize failures, implement containment measures and partner with design, manufacturing, quality and reliability teams to root cause and implement corrective actions.
Develop tools, flows and methodologies to continuously improve and automate the testing life cycle.
Requirements:
Minimum qualifications:
Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
4 years of experience in test engineering.
Experience in pre-silicon validation, test content generation, ATE program development, and post-silicon enabling from New Product Introduction (NPI) through High Volume Manufacturing (HVM).
Experience in Python, Java, C# or C/C++ and Advantest or Teradyne ATE platforms.
Experience with ASIC test methodologies (e.g., mbist, atpg, dft serdes, sensors).
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
10 years of experience in test engineering, including product engineering.
Experience with CPU/GPU SoC architecture, design, validation and debug.
Experience in advanced testing methodologies and data analysis, including system to tester correlation, yield and test time analysis and improvement, etc.
Expertise in developing automations for pre-silicon verification and post-silicon test-generation/test-program domains.
Ability to venture into, and improve, all aspects of post-silicon testing from definition to realization.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8843305
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior CPU Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, and system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning and test execution to collecting and closing coverage.
Responsibilities:
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
8 years of experience with creating and using verification components and environments in standard verification methodology.
Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, or a related field.
3 years of experience creating and using verification components and environments in standard verification methodology.
Experience with verification techniques, and the full verification life cycle.
Experience with performance verification of ASICs and ASIC components.
Experience with Application-Specific Integrated Circuit (ASIC) standard interfaces and memory system architecture.
Knowledge of CPU/Processor architectures (e.g., pipeline, cache, memory subsystem, instruction sets, exceptions) like ARM, X86 or RISC-V, is highly beneficial for verifying processor cores or IP blocks.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8843269
סגור
שירות זה פתוח ללקוחות VIP בלבד
סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Design Engineer, Edge AI, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work to shape the future of an Edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive distributed inference technology that powers real-time systems where latency and reliability are mission-critical.
You will be part of a team that pushes boundaries, developing robust, autonomous solutions that define the next generation of intelligent infrastructure and hardware for the edge. You will contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy complex AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our platforms, we make our product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Lead a complex ASIC subsystem.
Understand how it interacts with software and other ASIC subsystems to implement groundbreaking data center.
Define high-performance hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
3 years of experience with RTL development for ASIC subsystems using Verilog.
Experience with speed interfaces such as PCIe, InfiniBand, and their low latency, security, and reliability principles.
Experience with micro architecture, design, verification, logic synthesis, and timing closure.
Preferred qualifications:
Experience with scripting languages (e.g., Python or Perl).
Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
Knowledge of high performance and low power design techniques.
Knowledge of FPGA, emulation platforms, and SoC architecture.
Knowledge of assertion-based formal verification.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8843190
סגור
שירות זה פתוח ללקוחות VIP בלבד
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