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You will be responsible to create analysis tools to assist in architecture exploration. You will define and simulate CPU features and develop supporting tool chains including simulators, analysis tools, compiler, etc.. You will collaborate with SW and algorithm teams as well as implementation teams to define and build efficient CPUs that integrate seamlessly into various subsystems.
Responsibilities
Work with SW and algorithm teams for optimization and customization of ISAs, CPU architecture, and micro architecture features
Create and analyze benchmarks for CPU and SOC subsystem architectures
Develop architectural and performance simulators
Define and develop toolchain infrastructure

In this visible role, you will be responsible for defining DV methodologies, test-bench infrastructure, and for project execution for the next generation high-speed interfaces to enable groundbreaking I/O connectivity solutions for product lines.
You will have regular interaction with Architecture, Design and SW teams, and the opportunity to influence our future products.
The people who work here have reinvented entire industries with all hardware products. The same passion for innovation that goes into our products also applies to our practices - strengthening our dedication to leave the world better than we found it. Join us to help deliver the next groundbreaking products.
Description
You will develop verification test plans, tools, test benches, protocol monitors, and high-coverage stimulus vectors. Apply advanced techniques to achieve verification with the highest quality, productivity, and time-to-market. You will work closely with the design team to ensure timely delivery of quality designs. Working with methods to accelerate verification time. Involvement in Post-Silicon Validation.

In this highly visible role, you will be at the centre of a System-on-Chip design effort. collaborating with all disciplines, with a critical impact on getting functional products to millions of customers quickly
Description
Lead the complete DFT solutions in a chip design by working with chip DFT team to document DFT specifications, and define the SoC test interface Develop and implement DFT architecture Work with the validation team to verify DFT implementations and implement design changes Generate structural test vectors, analyze and improve coverage Work with designers on STA, physical, power and logical issues Work with Test Engineers to bring up test vectors on silicon

We are looking for talented engineers to join the Pre-silicon Verification team and help us technically lead the challenges of the next decade, developing a semiconductor platform based on revolutionary architecture, and taking part in the development of cutting-edge products within a disruptive system architecture.
Youll have the opportunity to work on the technologies that power the worlds largest cloud provider, in a dynamic, open, and fast-paced environment.

Required DFT Engineer , Nitro Team
Join our innovative semiconductor engineering team and help shape the future of cloud computing infrastructure. As a DFT Engineer at Annapurna Labs, you'll be instrumental in developing groundbreaking chip technologies that power the world's largest cloud platform. Your expertise will directly contribute to creating revolutionary semiconductor solutions that drive technological advancement and transform how global businesses leverage cloud services.
Key job responsibilities
* Develop comprehensive Design-for-Testability (DFT) strategies for advanced semiconductor platforms
* Collaborate with cross-functional engineering teams to ensure robust chip design and verification
* Generate and optimize test patterns using advanced methodological approaches
* Conduct detailed chip bring-up and lifecycle management processes
* Contribute to architectural definition and logic design for revolutionary semiconductor technologies
A day in the life
Your day will be dynamic and collaborative, involving deep technical problem-solving across multiple engineering domains. You'll engage with chip design, verification, and testing teams, translating complex architectural concepts into tangible semiconductor innovations. Expect to dive into intricate design challenges, develop sophisticated test methodologies, and contribute to cutting-edge product development.

We are looking for talented engineers to join the Pre-silicon Verification team and help us technically lead the challenges of the next decade, developing a semiconductor platform based on revolutionary architecture, and taking part in the development of cutting-edge products within a disruptive system architecture.
Youll have the opportunity to work on the technologies that power the worlds largest cloud provider, in a dynamic, open, and fast-paced environment.

we are a global leader in autonomous driving technologies and advanced driver-assistance systems (ADAS). Our cutting-edge solutions, including the EyeQ chip, our company SuperVision, our company Drive, and our company Chauffeur, leverage computer vision and machine learning to enhance vehicle safety and enable self-driving capabilities. Integrated into millions of vehicles worldwide, our technology is redefining the automotive industry and driving the evolution towards smarter, safer, and more autonomous mobility. We are seeking a skilled and driven Algorithm Team Lead to research, develop, and deploy state-of-the-art lidar based techniques that deliver world-class results, enabling the safe development of Autonomous Driving features and Advanced Driver Assistance Systems. ** This position requires on-site presence at our Jerusalem office one day per week.
What will your job look like:
As an Algorithm Team Lead, you will guide a team of talented developers to:
Design, develop, and implement lidar based algorithms in both C++ and python to solve complex problems
Collaborate with cross-functional teams to understand requirements and deliver robust solutions
Conduct research, evaluate existing models and techniques, and propose innovative approaches to improve algorithm performance and accuracy
Optimize existing algorithms for better performance and scalability.

we are looking for a skilled and motivated SW Quality and Test Architect for the Platform OS Department. The Platform OS team of our company is leading a global effort of making the Linux OS as the Automotive Safety OS that will fuel the Autonomous Vehicle and the whole automotive industry. As the technical lead and architect for Quality and Test aspects of the OS teams, you will be contributing to the overall qualification effort of our company while collaborating with OS development teams and architects
What will your job look like:
Work with the system and SW architecture teams closely.
Review and analyze all functional SW requirements from OS features and write the relevant testing and quality requirements for development teams.
Define the key performance indicators and the methodology of measuring and tracking them.
High level design of test scenarios.
Review test design and implementation with development teams.
Define functional requirements from the CI/DevOps teams to satisfy the OS quality needs.
Track the integration between the CI and OS tests.
Manage quality indicators like code quality and coverage indicators.
Mentor OS teams for quality programing and proper testing.
Track and analyze bug escapes on a continuous basis to improve testing coverage and overall quality.
Daily tracking of test coverage, resource utilization and testing time.

As a Quality and Reliability (Q&R) Engineer, you will lead the qualification and long-term reliability of advanced System-on-Chip (SoC) and RF semiconductor products for automotive applications. Youll work across digital and RF domains to ensure robust performance and compliance with industry standards.
What will your job look like:
Define and manage Quality and Reliability specifications, simulations, and qualification plans for SoC and RF die and package.
Plan and execute automotive-grade qualifications per standards such as AEC-Q100, JEDEC JESD22, and IATF 16949.
Design and implement die-level and package-level stress tests.
Select and prepare electrical, environmental, and mechanical test platforms for reliability testing.
Define requirements for Pre-Si Q&R (e.g. ESD, LU, EM, IR drop), Design-for-Test (DFT), electrical characterization, and Post-Si Q&R testing of digital, mixed-signal and RF SoCs.
Collaborate extensively with internal design teams, external subcontractors, and outsourcing partners (OSATs).
Lead failure analysis, reliability modeling, and corrective action processes (e.g., 8D, FMEA, FMEDA).
Document and certify automotive standards compliance, including PPAP/APQP deliverables.

We are looking for a FPGA Design Engineer.
What you will be doing:
Design and implement digital logic using VHDL for FPGAs (Xilinx, Altera).
Define and develop FPGA architectures based on system requirements.
Simulate and verify functionality at module and system levels.
Integrate IP cores and develop custom modules for data acquisition(ADC,DAC) ,communication protocols and control logic.
Collaborate with hardware, software, and verification teams to ensure robust integration.
Conduct hardware bring-up and debug using oscilloscopes, logic analyzers, and on-chip tools (ILA, SignalTap).
Document design specifications, test plans, and verification reports

We are looking for a highly motivated and professional senior physicist to lead and perform research and development at the interface of physics and medicine, in the rapidly developing field of TTFields.
Our physics group is leading an effort to develop a new field of research: Tumor Treating Fields (TTFields) dosimetry and treatment planning, and currently specializes in numerical simulations, biophysics research, experimental research, advanced algorithms, and numerical/clinical data analysis.
This is a full-time position, located at our R&D center, Haifa, Israel
ESSENTIAL DUTIES AND RESPONSIBILITIES:
Conduct research into the distribution of TTFields within the body using both electromagnetic and heat transfer simulations
Develop algorithms and infrastructure to support simulations and analysis of simulation results and clinical data.
Participate and support team efforts to develop the next generations of devices and treatment planning platforms for TTFields therapy.
Participate in research and development collaborations with internal groups of engineers and scientists, and with external researchers from academia.
Present results at internal meetings, seminars, and external scientific conferences; contribute to writing scientific papers and patent applications.

We are seeking a highly motivated, energetic, Software Engineer to support our Silicon Photonics Engineering group in Haifa, Israel.
Development occurs in a dynamic and challenging global multi-site environment. However, this is an individual contributor position reporting to the SiPh Engineering Manager in North Reading.
The ideal candidate will play a pivotal role in our dynamic team and will participate in developing complex test solutions for the emerging silicon photonic market at all stages of fabrication, from wafer probe to packaged test. This is a fantastic opportunity to contribute to innovative projects in the field of instrumentation
Utilize extensive C# experience to design, develop, and implement high-quality software instrumentation solutions
Collaborate with cross-functional teams to analyze requirements and deliver robust software applications
Develop scalable, high-performance, high-quality, extensible and maintainable software
Python knowledge is a plus, contributing to the versatility and adaptability of the development team

we are looking for a SoC / IP Architect to shape the next revolution in electronics!
Responsibilities

Define and design architecture: Create the overall SoC/IP architecture based on product and customer requirements and define detailed technical specifications.
Collaborate with cross-functional teams: Work with a variety of teams, including logic design, verification, firmware architecture and development teams, and physical design, to ensure successful execution.
Lead technical discussions and architectural reviews, guiding design and verification teams to deliver scalable, high-quality implementations.
System-level integration: Ensure seamless hardware-software co-design by working on aspects like control paths, interrupt schemes, and debug infrastructure.
Drive architectural decisions that optimize scalability, and future readiness for next-generation applications.
Act as Functional Safety manager, leading the definition, execution and oversight of functional safety strategy and processesensuring compliance with standards (such as ISO 26262), driving hazard and risk analyses, coordinating cross-functional teams, and embedding safety-culture across product development