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we are looking for a Senior Logic Design Engineer to join the ride as we spearhead the next revolution in electronics and lead the IP Integration Enablement.
Responsibilities

Customer-Centric Integration Leadership

Act as the voice of the customer in internal R&D reviews, advocating for integration simplicity, design compatibility, and customer usability.
Identify and address integration challenges early in the development cycle to ensure seamless adoption by customer design teams.
Integration Infrastructure & Collateral

Define and oversee all integration-related deliverables, ensuring quality, consistency, and alignment with customer integration needs.
Review and contribute to the development of collateral, including:
o Lint, CDC, RDC and IPXACT views

o Register maps, ICL and PDL files

o Simulation and emulation views

o Integration testbenches and verification collaterals

Out-of-the-Box Integration Benchmark & Regression

Develop and maintain an out-of-the-box environment to evaluate IP integration from the customers perspective.
Validate end-to-end IP Integration in representative SoC contexts using the Proteus IP integration flow as described in the integration guide.
Develop and maintain integration regression tests to ensure integration KPIs are consistently met.
Cross-Functional Collaboration

Train and mentor Application Engineers on the Proteus IP integration playbook, ensuring consistent and effective deployment across customer projects.
Provide expert support for complex integration challenges escalated through the field teams.
Gather structured feedback from Application Engineers and customers to continuously refine integration methodologies and improve the overall integration experience.

we are looking for a Senior VLSI Verification Engineer to join the ride as we spearhead the next revolution in electronics!
Responsibilities

Develop and maintain advanced verification environments using SystemVerilog and UVM, ensuring scalability, configurability, and reusability across multiple IPs.
Design, implement, and execute comprehensive testbenches and random test suites to validate functional correctness, robustness, and corner-case behavior of complex IP within various SoC integration environments.
Drive coverage closure by defining, collecting, and analyzing code and functional coverage metrics; identify verification gaps and ensure complete validation of feature sets prior to sign-off.
Lead debug and root-cause analysis efforts in collaboration with senior verification and design engineers, leveraging carefully crafted logs, waveform analysis and assertions to isolate and resolve design or environment issues.
Collaborate closely with architecture, design, and firmware teams to ensure verification completeness, alignment with design intent, and seamless integration at the system level.
Contribute to methodology and infrastructure improvements, including reusable UVM components, automation scripts, and best practices that enhance team efficiency and verification quality.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a CPU Workload Analysis Researcher within our company Cloud's MSCA organization, you will be integral to developing silicon solutions powering our company's direct-to-consumer products. You will join a Research and Development team focused on analyzing and profiling workloads requirements within the company Cloud environment. Your role will involve conducting in-depth research on CPU optimization, feature development, and ML usages over compute platforms, contributing to identifying key areas of investment and future opportunities. This role offers a unique opportunity to perform groundbreaking research with a significant impact on both research methodologies and industry products, within the server chip architecture team. Your work will directly influence the next generation of hardware experiences for millions of our company users and Cloud customers.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan and execute detailed analysis of CPU workloads within the company Cloud infrastructure, analyze trends and map future requirements.
Collaborate closely with architecture and modeling owners to understand design specifications and identify critical scenarios related to CPU performance and efficiency.
Develop and implement custom workload generation tools and methodologies to simulate real-world usage patterns on our company Cloud platforms.
Analyze the impact of machine learning applications on CPU usage, identifying opportunities for optimization and feature enhancements.
Lead the investigation and development of metrics to measure CPU performance and efficiency, presenting findings to stakeholders and contributing to strategic decisions.

Board Design Engineer (5881) We are seeking an experienced Board Design Engineer to develop advanced electronic boards for complex systems. The role entails full ownership of the board design process, encompassing requirements and schematics, as well as testing and integration.