דרושים » חשמל ואלקטרוניקה » Power Micro-Architecture Engineer

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Staff / Principal ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects.
As a Staff / Principal ASIC Design Engineer, you won't just build chips-you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Design Ownership & Implementation
Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support
Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions
Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams
Quality Assurance & Design Optimization
Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient
Apply design techniques to meet PPA (Power, Performance, Area) targets
Contribute to design quality through verification and validation activities
Methodology Innovation & Collaboration
Participate in design methodology improvements and tool automation initiatives
Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter
Collaborate effectively across teams to ensure seamless integration.

The System-On-Chip (SOC) group is looking for a strong RTL Design Engineer to own the SOC clocking logic for our next-generation networking chips. Clocks are the backbone of the SOC. In this role you will own the clock generation, distribution, and control logic for the entire chip - PLL and reference clock integration, clock muxing and dividers, glitchless switching, clock gating, reset synchronization, and the clock domain crossing infrastructure that every unit on the die depends on.

This is an RTL design role, not a circuit or transistor-level design role. You will translate micro-architecture specifications into high-quality synthesizable RTL, and drive that RTL through to silicon in close partnership with the micro-architecture, Design Verification, and Physical Design (backend) teams. You will also interact with CAD, Package Design, Software, and DFT teams.

What you'll be doing:

Owning the SOC clocking logic end to end: writing synthesizable Verilog/SystemVerilog RTL for clock generation, distribution, muxing, division, glitchless switching, gating, and reset synchronization, from micro-architecture specification through tape-out.

Defining and implementing the SOC clock and reset architecture together with the micro-architecture team - collecting clocking requirements from every unit on the chip and turning them into a coherent, verifiable design.

Owning clock domain crossing infrastructure and CDC closure across the SOC.

Partnering with the micro-architecture team to review specifications, close on design intent, and provide feedback on implementation cost, timing, area, and power.

Working hand-in-hand with the Physical Design (backend) team on clock tree implementation and constraints, partitioning, floorplan and timing feedback, trial synthesis, congestion and timing convergence, and physical design readiness.

Supporting Software and firmware teams on clock programming sequences, DVFS, and low-power/clock-shutdown flows.

Driving design quality: lint, CDC/RDC, formal checks, synthesis QoR, connectivity and structural checks.

Supporting SOC-level chip build and assembly, and developing/deploying automation flows that make RTL integration and design quality checking repeatable and scalable.

Supporting emulation, firmware, and post-silicon bring-up customers of your design.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Junior ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects.
As a Junior ASIC Design Engineer, you won't just build chips - you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Design Ownership & Implementation
Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support
Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions
Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams
Quality Assurance & Design Optimization
Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient
Apply design techniques to meet PPA (Power, Performance, Area) targets
Contribute to design quality through verification and validation activities
Methodology Innovation & Collaboration
Participate in design methodology improvements and tool automation initiatives
Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter
Collaborate effectively across teams to ensure seamless integration.

We are looking for a best-in-class Senior Full-Chip Verification Engineer with a strong infrastructure mindset to join our Networking Silicon team. In this role, you will be responsible for the development and verification of our next-generation NICs at the system level, while also driving the evolution of the simulation infrastructure powering our verification flows. You will contribute to the architecture of high-speed communication devices by driving full-chip verification execution for the networking solutions powering the world's most advanced data centers, in a meaningful, growing environment where you make a huge impact in a technology-focused company.

What you'll be doing:

Simulation Infrastructure & Acceleration: Identify bottlenecks in the verification flow and engineer creative solutions - building frameworks, optimizing regressions, and accelerating simulation throughput through innovative tooling.

Multi-Language Development: Work across a diverse technology stack (SystemVerilog/UVM, Specman, Python, C/C++, scripting) - writing code and solving problems at every layer, from RTL testbenches to infrastructure utilities and automation.

System-Level Debug & Analysis: Gain a strong understanding of chip micro-architecture and features, investigate, debug, and resolve cross-block issues to guarantee feature correctness and compliance.

AI-Enhanced Development: Accelerate development by leveraging cutting-edge AI coding tools and frameworks - applied to both verification and infrastructure challenges.

Cross-Team Collaboration: Work closely with multiple teams within organizations such as Architecture, u-arch, Firmware and all units inside the NIC.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Junior Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.
As a Junior Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow-you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Physical Implementation & Execution
Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
Own macro-level implementation with deep hands-on experience in floorplanning and complex routing
Signoff & Design Integrity
Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
Ensure first-pass silicon success through rigorous signoff flows and analysis
Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness
Methodology Development & Cross-Functional Collaboration
Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation
Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity
Leverage scripting and automation to make engineering environment faster and more robust.

Our networking is a world-leader in building the most powerful supercomputers in the world which drive the AI and HPC industry. These rely on high performant network ASICs which connect GPUs at scale for efficient data transfer and compute. We are looking for a hardware performance modeling architect to join our team and build a network simulator used for the design, optimization and exploration of our future networking chips. The role is cross-disciplinary, collaborating with hardware and software teams across the wider company. You will solve complex problems, develop innovative solutions and be instrumental in determining the architecture of our next generation networking solutions.

What you'll be doing:

Define the Network Adapter chip architecture end to end from the market requirements through design and all product life cycles (post/pre-silicon, on deployments). Work with related industry standards & customers on deploying your tech.

Collaborate with teams across teams (physical design, logic design, system software, firmware, applications)

Develop cycle-accurate simulation components to evaluate and analyze micro-architecture and architectural options.

Explore innovative ideas to improve and optimize our chip systems performance.

Serve as a focal point within the organization and distribute the knowledge that you acquire.

We are looking for a Full-Chip verification & Integration Engineer to join our FullChip Switch Silicon team. As part of NVIDIAs Networking business unit, you will work alongside passionate and highly skilled engineers building the next generation of state-of-the-art switch silicon chips. This is a unique opportunity to grow in a technically rich environment and gain broad system-level exposure, and contribute to cutting-edge devices that deliver world-class bandwidth, throughput, and latency.

In this role, you will help integrate and validate complex full-chip flows at the system level, working across multiple engineering domains and learning how advanced silicon products come together from architecture to execution.

What you'll be doing:

Work in a Full Chip verification team that is responsible to integrate and verify our Switch products at system level.

Work closely with multiple teams within the organizations such as Architecture, u-arch, Firmware and all switch units and Ips.

Play a key role in validating the most complex end-to-end chip flows, gaining hands-on experience with system behavior, cross-block interactions, and real product-level scenarios.

Use modern AI-powered engineering tools and automation techniques as part of your day-to-day development and debug workflow.

Learn from experienced engineers in a collaborative environment that encourages technical growth, ownership, and continuous improvement.

Required IP Design Lead, Networking, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will use Application-Specific Integrated Circuit (ASIC) design to be part of a team that creates the System-on-a-Chip (SoC) design cycle from start to finish. You will collaborate with design and verification engineers in projects, creating architecture definitions with Register-Transfer Level (RTL) coding, and running block level simulations. You will contribute in ASIC designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis and more to specify and deliver high-quality SoC/RTL. You will also solve technical issues with innovative micro-architecture and practical logic solutions, and evaluate design options with performance, power, and area in mind.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next-generation of our platforms, we make product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Own Networking Internet Protocols (IP's) Design team including definition, implementation and deployment.
Establish IP development methodologies sharing unified blocks within the IP design team.
Define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Demonstrate technical involvement throughout the entire Intellectual Property (IP) development cycle, ensuring seamless integration into System-on-Chip (SoC).
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks.

Required SoC Quality and Reliability Engineer, Cloud
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Our data centers are the most advanced in the world. In this role, you will help build the state-of-the art SoCs that power these data centers by driving quality and reliability processes from the Integrated Circuit perspective. This is an opportunity to create silicon and follow it into the field (and back!) to drive improvements for the next-generations of chips.
In this role, you will understand Integrated circuit (IC) flows, wafer processing, testing, qualification, yield, reliability, and failure analysis. You will work with various cross-functional teams to develop quality and reliability specifications, develop and deploy design guidelines, and develop and execute and test plans. Within the larger organization you will collaborate with global hardware quality and reliability teams, silicon design, validation and engineering teams.The AI and Infrastructure team is redefining whats possible. We empower customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity.
Responsibilities
Drive the strategic definition and development of Design-for-Reliability (DfR) guidelines, collaborating with cross-functional subject matter experts to integrate reliability into early design stages.
Define and lead the development of qualification hardware and test methodologies, managing internal teams and external vendors to ensure robust silicon and package verification.
Execute comprehensive silicon and package qualification programs (including HTOL, ELFR, ESD/LU, b/HAST, etc.) and conduct in-depth failure analysis to resolve quality issues.
Extract and analyze large-scale data from qualification programs, high-volume manufacturing, and field returns to identify failure mechanisms and trends for yield and reliability optimization.
Develop and implement physics-based statistical Quality and Reliability models (e.g., ELF, TDDB, NBTI) to predict device failure mechanisms and lifetime behaviors.

We are looking for an experienced DFT Engineer to join an exceptional team of DFT experts to develop the next generation DFT technologies.

As a DFT engineer at the networking group, you will participate in definition and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and sophisticated products, our DFT solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.

What you'll be doing:

In this position, you will be responsible for defining, coding and integrating sophisticated DFT components into various projects and using state-of-the-art technologies.

As a member of our DFT design team, you will participate in defining various DFT features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.

Strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.