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לפני 13 שעות
חברה חסויה
Location: Yokne`am and Tel Aviv-Yafo
Job Type: Full Time
Our networking is a world-leader in building the most powerful supercomputers in the world which drive the AI and HPC industry. These rely on high performant network ASICs which connect GPUs at scale for efficient data transfer and compute. We are looking for a hardware performance modeling architect to join our team and build a network simulator used for the design, optimization and exploration of our future networking chips. The role is cross-disciplinary, collaborating with hardware and software teams across the wider company. You will solve complex problems, develop innovative solutions and be instrumental in determining the architecture of our next generation networking solutions.

What you'll be doing:

Define the Network Adapter chip architecture end to end from the market requirements through design and all product life cycles (post/pre-silicon, on deployments). Work with related industry standards & customers on deploying your tech.

Collaborate with teams across teams (physical design, logic design, system software, firmware, applications)

Develop cycle-accurate simulation components to evaluate and analyze micro-architecture and architectural options.

Explore innovative ideas to improve and optimize our chip systems performance.

Serve as a focal point within the organization and distribute the knowledge that you acquire.
Requirements:
What we need to see:

BSc/MSc in Electrical Engineering, Computer Science from a known university.

Experience in developing simulation models.

4+ years of experience in a relevant role as chip architecture or system integration

Knowledge and understanding of computing and networking systems.

Strong debug skills.

A can-do attitude and high energy with leadership and excellent interpersonal skills and possess the ability to learn complex concepts in a fast pace environment.

Utmost passion for attention to details in design and a high focus on design quality.


Ways to stand out from the crowd:

Experience and love for system architecture, CPU/GPU/Memory/Storage/Networking.

We are widely considered to be one of the tech worlds most desirable employers.

Master's degree in Electrical Engineering, Computer Science or related technical field.

5+ years of relevant practical experience.

Experience with network simulation tools (omnet, ns3, sst, gem5).
This position is open to all candidates.
 
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1 ימים
Location: More than one
Job Type: Full Time
We are seeking a highly motivated High-Performance System Architect to join our team of experts and help shape the future of high-performance and ML / AI computing. Our next-generation NVL systems will be at the forefront of connecting and powering the world's most advanced compute clusters, which would be used to train the most advanced AI models such as GPT and DeepSeek. As a high-performance system architect, you will have the opportunity to work on some of the most cutting-edge technology and help to drive the innovation of our next generation networks that will be used by top researchers and engineers around the world.

What youll be doing:

Define the NVL system architecture end-to-end, by internal requirements and customers requirements through all product life cycles (post/pre silicon, on deployments).

Research various of solutions to enable the next large-scale-high-performance computing clusters. The position spans over various layers from algorithms, software, firmware, and HW.

Collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and research teams, to ensure the successful execution of the project.
Requirements:
What we need to see:

B.Sc, M.Sc, or Ph.D degree in Computer Science, Computer Engineer, or Electrical Engineer.

At least 5 years of industry or research experience in computer networks.

Excellent understanding of large-scale networks behavior and the effect of distributed computing workloads effect on the network.

Experience in developing models for simulations, analyzing simulation results and development of optimization algorithms.

Possess strong managerial, problem solving and critical thinking skills.

Ability to work and operate in a highly dynamic environment.

Partner with multiple groups in the organization.


Ways to stand out from the crowd:

Good knowledge in network protocols - such as InfiniBand, IP, TCP and RoCE and network topologies.

Good knowledge in Python, C++.

Familiarity with HPC environments, routing algorithms, Omnet++ and NS3 simulation environments.
This position is open to all candidates.
 
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1 ימים
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are looking for a talented and experienced Firmware Architect to join our Network Adapter Firmware team in Yokneam.

As part of our technical leadership team, you will define the firmware architecture for next-generation networking devices and drive design of innovative technologies powering the world biggest AI Platforms, cloud computing, HPC, storage, and automotive platforms.

The Network Firmware team develops cutting-edge firmware that enables the world's largest cloud providers and enterprises to deliver high-performance, reliable, and secure networking solutions. Working alongside exceptional engineers across the globe, you'll thrive in a dynamic, collaborative, and fast-paced environment while solving some of the industry's most challenging technical problems.

What you'll be doing:
Collaborate closely with Hardware, Software, and System Architecture teams to define end-to-end solutions.
Define the firmware architecture for new products and features at the core of our NIC firmware.
Lead the design and implementation of strategic technologies, including functional safety, security, and next-generation networking capabilities.
Mentor and technically guide R&D engineers throughout architecture, design, and implementation.
Drive technical direction across multiple teams while ensuring scalable, maintainable, and high-quality firmware architecture.
Requirements:
What we are looking for:
B.Sc. in Computer Science, Computer Engineering, Electrical Engineering, or equivalent practical experience.
10+ years of firmware or embedded software development experience.
4+ years of technical leadership experience (Technical Lead, Architect, or Technical Manager).
Excellent understanding of algorithms, data structures, and software design principles.
Strong analytical, debugging, and problem-solving skills.

Ways to stand out from the crowd:
Experience with networking protocols and high-performance networking.
Experience developing real-time or embedded systems.
Experience designing large-scale firmware architectures.
Familiarity with Agile development methodologies.
Experience with security technologies or safety-critical systems.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Machine Learning Hardware Architect, Hardware, Software Co-Design, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a Machine Learning Hardware Architect within the Co-design team, you will serve as a technical lead bridging model architecture innovation and next-generation hardware design. Operating at the highest levels of AI research and engineering, you will define the goal and architectural roadmap for our future machine learning serving and training capabilities. You will guide the integration of ML research such as massive-scale foundation models with advanced silicon architectures to create industry-leading, high-performance, and power-efficient accelerators.
Responsibilities
Define and drive the technical roadmap and architecture for the hardware/software stack to ensure exceptional performance for ML models. Act as the technical liaison across research, software, and hardware teams, steering model architecture innovation to maximize scaling, quality, and hardware efficiency.
Architect next-generation configurable simulation frameworks and performance models, setting the organizational standard for evaluating complex microarchitectural decisions. Drive high-stakes choices regarding Power, Performance, Area (PPA) and buildability for future chip and system architectures, expertly balancing long-term technological trends with strict product delivery timelines.
Guide system-level performance analysis across highly distributed ML systems, innovating new methodologies to optimize and balance compute, memory bandwidth, and inter-chip network requirements. Their leadership will directly shape the future of high-performance AI infrastructure and hardware-software co-design.
Manage cross-functional partnerships across hardware, compiler development and ML teams.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
12 years of experience in computer architecture, chip architecture, or hardware-software co-design.
Experience architecting and developing software systems in C++ or Python for performance modeling, simulation, or system analysis.
Preferred qualifications:
Masters degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture.
Experience as a lead architect managing multi-generational hardware solutions or performance optimizations for massive-scale ML training and inference.
Experience in semiconductor technologies, industry trends, and the future trajectory of process, memory, interconnects, and packaging.
Experience with deep learning frameworks (e.g., TensorFlow, PyTorch) and deep understanding of their underlying execution models.
This position is open to all candidates.
 
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1 ימים
Location: Tel Aviv-Yafo
Job Type: Full Time
We are seeking a Network Solution Verification Manager to join our R&D organization, leading the validation of our customer-facing networking solutions at scale using a state-of-the-art End-to-End (E2E) simulation cluster environment.

In this role, you will build and lead a team of validation engineers, owning the strategy, methodology, and execution of simulation-based validation frameworks that ensure our networking solutions meet the highest standards of quality, scale, and real-world applicability before reaching customers.


What you'll be doing:
Leading and managing a team of network validation engineers responsible for end-to-end validation of our customer-facing networking solutions at scale, using a dedicated E2E simulation cluster environment.
Defining the overall validation strategy and roadmap - establishing simulation methodologies, test coverage frameworks, and quality gates that align with product milestones and customer use cases.
Pioneering the use of agentic AI flows within the validation organization - leading the team to design, build, and operate AI-driven agents capable of autonomously performing regression analysis, identifying coverage gaps, generating new test cases, and implementing validation code. These agentic workflows will continuously learn from simulation results and product changes, dramatically accelerating the team's ability to scale test coverage and respond to emerging quality signals without manual intervention.
Overseeing the design and continuous improvement of automated regression suites for networking protocols and large-scale simulation runs, ensuring scalable, repeatable, and high-confidence validation outcomes.
Establishing a rigorous regression analysis culture - guiding the team in identifying trends, root causes, and systemic coverage gaps, and ensuring timely resolution in collaboration with engineering stakeholders.
Serving as the primary validation partner to Design, Architecture, and NCS teams - translating solution requirements into simulation scenarios, providing early-cycle quality feedback, and influencing product direction.
Analyzing customer-reported networking solution issues, driving test gap analysis, and ensuring robust regression coverage that prevents recurrence.
Staying current with emerging networking standards, simulation technologies, and industry best practices to continuously evolve the team's validation capabilities.
דרישות:
What we need to see:
B.Sc. degree or equivalent experience in Computer Science, Electrical Engineering, Computer Engineering, or a related field.
3+ years of experience in a leadership or management role, leading software or hardware validation/test engineering teams.
7+ years of overall experience in network validation, network testing, or systems verification.
Proven track record of building and executing test automation strategies for network or distributed systems at scale, with hands-on background in Python-based automation.
Strong understanding of regression analysis methodologies - ability to drive actionable conclusions from large-scale test result datasets and translate them into engineering improvements.
Demonstrated ability to collaborate cross-functionally with architecture, design, and product teams in a fast-paced, multi-timezone environment.
Strong verbal and written communication skills, with experience presenting validation strategies and quality metrics to senior leadership.


Ways to stand out from the crowd:
Deep understanding of networking protocols and architectures (e.g., BGP, EVPN, VXLAN, RDMA/RoCE, Ethernet, IP routing, L2/L3 switching).
Experience with network simulation or emulation environments (e.g., Containerlab, GNS3, SONiC testbeds, or equivalent platforms) and the ability to guide teams in leveraging them effectively.
Experience managing validation of data center networking solutions or hyperscale network environments (spine-leaf, fat-tree, or Clos top#EN המשרה מיועדת לנשים ולגברים כאחד.
 
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1 ימים
Location: Tel Aviv-Yafo
Job Type: Full Time
In this role, you will be a key contributor to defining the architecture and improving network performance for AI and High Performance Computing (HPC) workloads. You will be responsible for modeling advanced network topologies, configurations, logic and traffic patterns, and analyzing their effect on end to end performance. You will develop expertise in our simulation tools and contribute directly to their development road map and prioritization, develop core features in the simulator, and expose the capabilities to additional users. You will take part in complex architecture decisions, define and verify the modeling assumptions, and put them to the test vs. real HW and SW performance.

If you're passionate about tackling intricate challenges and contributing to comprehensive systems and working on innovative solutions, we want to hear from you.

What you'll be doing:

Analyze and model our AI and High Performance Computing offerings, deep dive into network behavior for training and inference and generate insights to directly impact the architecture of next-generations of AI systems. Conduct advanced network modeling, research and optimization using innovative simulation tools.

Implement modeling of advanced network topologies, configurations and traffic patterns which represent real life AI workloads, and analyze their effect on the systems performance. Actively develop the simulator software solution while contributing modular and scalable code.

Actively support the HW and SW development life cycles, map existing and candidate features into the simulation domain to enable their analysis, impact assessment and optimization.

Take full independent ownership of the performance modeling roadmap for a defined set of features. Interface directly with internal clients, communicate the analysis conclusions effectively and iterate on them. Drive projects from concept to completion.

Improve the quality of the simulation as a software product, ensuring robustness and reliability.
Requirements:
What we need to see:

BSc or above in Computer Science, Electrical Engineering, or a related field

5+ years of hands-on coding experience with strong proficiency in C++ and Python. You must be comfortable navigating, optimizing, and contributing to a complex, large-scale codebase.

End to end system perspective - capable of bridging the gap between hardware behavior, micro-architecture, and software performance (latency/throughput).

Project ownership capability with proven ability to lead technical initiatives, prioritize features, and manage project lifecycles autonomously with minimal supervision.


Ways to stand out from the crowd:

Strong background in communication networks technology. Deep understanding of Ethernet, NVLink, and/or Infiniband technologies, data center infrastructure, and network protocols.

Familiarity with discrete event simulators (e.g., OMNeT++, SystemC, or proprietary architectural simulators).

Advanced degree or experience focusing on computer architecture, algorithms, networking, or distributed systems.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Staff Architect, Digital Signal Processing, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Staff Engineer on the Digital Signal Processing team, you will be a technical leader responsible for architecting and developing the core algorithms that power our next-generation data center interconnects. You will leverage your expertise in communication theory, forward error correction (FEC), and modulation to design novel, low-complexity solutions that push the boundaries of speed and reliability.
In this role, you will not only define the technical direction for critical projects but also mentor other engineers and collaborate across hardware and software teams to bring your goal to life in silicon.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead the architecture, design, and implementation of digital signal processing (DSP) algorithms for high-speed optical communication systems. Drive the long-term technical roadmap for our signal processing and communication architectures by staying current with academic and industry trends.
Develop and analyze novel forward error correction (FEC) and modulation schemes to optimize for performance, power, and complexity tradeoffs.
Create comprehensive system-level models using tools like Matlab, Python, or C++ to simulate and validate algorithm performance.
Collaborate closely with logic design, verification, and software teams to ensure the successful implementation, integration, and bring-up of algorithms in custom silicon.
Provide technical leadership and mentorship to a team of DSP and communication systems engineers, fostering innovation and engineering excellence.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field or equivalent practical experience.
10 years of experience in digital signal processing, communication theory, and algorithm development.
Experience in the design and implementation of algorithms for communication systems, including FEC or modulation techniques.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience.
Experience in the theory and practical implementation of modern FEC codes (e.g., LDPC, staircase, polar codes) and advanced modulation formats.
Experience in designing and modeling high-speed optical communication transceivers or similar high-bandwidth systems.
Experience leading the development of algorithms from initial concept through to successful silicon production.
Strong publication record in conferences or journals in the field of communications or signal processing.
Excellent programming skills in Matlab for algorithm development, simulation, and analysis.
This position is open to all candidates.
 
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1 ימים
Location: Tel Aviv-Yafo
Job Type: Full Time
What you'll be doing:
Develop, model, and validate groundbreaking power and performance optimization techniques for network fabrics, components (NICs, Switches), and systems. Collaborate closely with cross-functional teams including silicon design, system architects, software/firmware engineers, performance analysts, thermal engineers, and AI researchers to ensure end-to-end power and performance optimization. You will determine strategies that successfully implement flawless performance and power efficiency in our ambitious projects!
Requirements:
What we need to see:
BSc or MSc or equivalent experience in Electrical Engineering, Computer Engineering, Computer Science or a related field
5+ years of relevant experience in network architecture, design, or performance analysis.
Solid understanding of power consumption dynamics in network hardware (NICs, switches, cables) and systems.
Proven experience in network architecture and design, particularly for large-scale systems (Data Center, HPC, AI Clusters).
Strong understanding of network protocols (Ethernet, InfiniBand, RoCE, TCP/IP) and their impact on performance and efficiency.
Demonstrable expertise in network performance analysis, bottleneck identification, and tuning.
Familiarity with the characteristics and network demands of AI/ML workloads
Utmost passion for attention to details in design and a high focus on design quality, particularly concerning power/performance trade-offs.

Ways to stand out from the crowd:
Advanced degree or equivalent experience in a related field.
Proven dedication to system-level power/performance trade-off analysis, especially in distributed computing or large-scale network environments.
Experience in power modeling, measurement techniques, or relevant tools for network components and systems.
Proficiency with network simulation tools (e.g., ns-3, OMNeT++, proprietary tools) or performance modeling frameworks.
Understanding of silicon-level power characteristics and optimization techniques.
This position is open to all candidates.
 
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05/07/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
We're looking for an exceptional senior Chip Design Engineer to join our Nitro team and help shape what comes next. You'll work alongside a world-class, fast-moving engineering team, take full ownership of critical IP blocks, and see your work deployed at a scale no other platform can match- powering hundreds of thousands of businesses across 190 countries.

If you want to build silicon that leads the cloud world, this is where it happens.

As a Senior Chip Design Engineer on the Nitro team, you will take full end-to-end ownership of one or more critical IP blocks within the product, guiding them from micro-architecture definition through RTL design, debug, synthesis, timing closure, and final sign-off before tape-out. Your work will ship in silicon that powers AWS at global scale.
You'll partner closely with the Verification and Emulation teams to shape test plans, review coverage, and close gaps early in the design cycle. Beyond your own IP, you'll collaborate across disciplines with Product Definition, Software, Physical Design, and Verification teams to deliver a fully integrated, production-ready chip.

Key job responsibilities
* Full ownership of one or more IPs within the product:
Micro-architecture definition.
RTL coding and debug.
Synthesis and timing closure.
Sign-off before tape-out.
* Supporting the Verification and Emulation teams: Test plan development, coverage review.
* Ensuring the chip meets quality and reliability standards.
* Collaborating with cross-functional teams, including Product Definition, Verification, Software, and Physical Design.
Requirements:
Basic Qualifications:
- 6+ years of experience in chip design.
- Hands-on experience in micro-architecture and RTL design (Verilog / System Verilog).
- Scripting expertise in C*, Perl, Python, or TCL.
- BSc in Computer/Electrical Engineering.
- Strong communication and collaboration skills.
- Strong leadership skills and ability to own complex units.

Preferred Qualifications:
- Strong knowledge of protocols (AXI, CHI, DDR, Networking, PCIe).
- Experience with Network-on-Chip (NOC) architecture.
- knowledge with coherent and non-coherent fabric design.
- Comprehensive SoC development cycle expertise (Synthesis, STA, CDC, Lint).
- Knowledge of Design Automation tools and techniques.
- Advanced degree in related technical field.
This position is open to all candidates.
 
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22/07/2026
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
We're looking for an exceptional senior Chip Design Engineer to join our Nitro team and help shape what comes next. You'll work alongside a world-class, fast-moving engineering team, take full ownership of critical IP blocks, and see your work deployed at a scale no other platform can match- powering hundreds of thousands of businesses across 190 countries.

As a Senior Chip Design Engineer on the Nitro team, you will take full end-to-end ownership of one or more critical IP blocks within the product, guiding them from micro-architecture definition through RTL design, debug, synthesis, timing closure, and final sign-off before tape-out. Your work will ship in silicon that powers AWS at global scale.
You'll partner closely with the Verification and Emulation teams to shape test plans, review coverage, and close gaps early in the design cycle. Beyond your own IP, you'll collaborate across disciplines with Product Definition, Software, Physical Design, and Verification teams to deliver a fully integrated, production-ready chip.

Key job responsibilities
* Full ownership of one or more IPs within the product:
Micro-architecture definition.
RTL coding and debug.
Synthesis and timing closure.
Sign-off before tape-out.
* Supporting the Verification and Emulation teams: Test plan development, coverage review.
* Ensuring the chip meets quality and reliability standards.
* Collaborating with cross-functional teams, including Product Definition, Verification, Software, and Physical Design.
Requirements:
Basic Qualifications
- 6+ years of experience in chip design.
- Hands-on experience in micro-architecture and RTL design (Verilog / System Verilog).
- Scripting expertise in C*, Perl, Python, or TCL.
- BSc in Computer/Electrical Engineering.
- Strong communication and collaboration skills.
- Strong leadership skills and ability to own complex units.

Preferred Qualifications
- Strong knowledge of protocols (AXI, CHI, DDR, Networking, PCIe).
- Experience with Network-on-Chip (NOC) architecture.
- knowledge with coherent and non-coherent fabric design.
- Comprehensive SoC development cycle expertise (Synthesis, STA, CDC, Lint).
- Knowledge of Design Automation tools and techniques.
- Advanced degree in related technical field.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8749919
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22/07/2026
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
We're looking for an exceptional senior Chip Design Engineer to join our Nitro team and help shape what comes next. You'll work alongside a world-class, fast-moving engineering team, take full ownership of critical IP blocks, and see your work deployed at a scale no other platform can match- powering hundreds of thousands of businesses across 190 countries.

As a Senior Chip Design Engineer on the Nitro team, you will take full end-to-end ownership of one or more critical IP blocks within the product, guiding them from micro-architecture definition through RTL design, debug, synthesis, timing closure, and final sign-off before tape-out. Your work will ship in silicon that powers us at global scale.
You'll partner closely with the Verification and Emulation teams to shape test plans, review coverage, and close gaps early in the design cycle. Beyond your own IP, you'll collaborate across disciplines with Product Definition, Software, Physical Design, and Verification teams to deliver a fully integrated, production-ready chip.

Key job responsibilities
* Full ownership of one or more IPs within the product:
Micro-architecture definition.
RTL coding and debug.
Synthesis and timing closure.
Sign-off before tape-out.
* Supporting the Verification and Emulation teams: Test plan development, coverage review.
* Ensuring the chip meets quality and reliability standards.
* Collaborating with cross-functional teams, including Product Definition, Verification, Software, and Physical Design.
Requirements:
Basic Qualifications
- 6+ years of experience in chip design.
- Hands-on experience in micro-architecture and RTL design (Verilog / System Verilog).
- Scripting expertise in C*, Perl, Python, or TCL.
- BSc in Computer/Electrical Engineering.
- Strong communication and collaboration skills.
- Strong leadership skills and ability to own complex units.

Preferred Qualifications
- Strong knowledge of protocols (AXI, CHI, DDR, Networking, PCIe).
- Experience with Network-on-Chip (NOC) architecture.
- knowledge with coherent and non-coherent fabric design.
- Comprehensive SoC development cycle expertise (Synthesis, STA, CDC, Lint).
- Knowledge of Design Automation tools and techniques.
- Advanced degree in related technical field.
This position is open to all candidates.
 
Show more...
הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8749950
סגור
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