דרושים » הנדסה » ATE Design Engineer (IL)

Requirements:
Minimum Skills And Experience
Experience with ASIC FE logic design. RTL coding, FE tools and signoff.
Experience in complex design (data-path or control-path)
Required Skills And Experience
BS/MS in Electrical and/or Computer Engineering with 8 to 10 years of experience.
Knowledge and experience in CPU or micro-controller designs (multi pipeline)
Processor system knowledge includes basic understanding of SoC systems as well as operating system software is a plus.
Great communication & teamwork skills.
Minimum Qualifications
Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field.
References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

Requirements:
BSc / MSc / PhD in Electrical Engineering, Computer Engineering, or a related field.
7+ years of experience in VLSI / ASIC design, chip architecture, or micro-architecture of complex blocks.
Strong background in high-speed networking systems such as:
o Ethernet Switches
o NPUs
o NICs
o Traffic Managers
o Fabric Switches
o High-performance processors
Skills
What Were Looking For
Excellent written and verbal communication skills in English.
Strong collaboration skills and the ability to work effectively across teams and disciplines.
Independent, self-driven, and capable of deep technical ownership.
Passion for innovation and cutting-edge technology.
Highly motivated with a proactive mindset.

Requirements:
MSc or BSc in computer science/EE or area related to computer architecture, or equivalent research experience in industry
At least 7 years of relevant research and development experience in industry and academia in the following areas:
Computer architectures: instruction set architecture, microarchitecture, cache sub-system, memory sub-system, NOC, interconnect
Workload characterization and analytical model generation
System Modelling and emulation of HW.
Simulation of Software workloads and Software applications on HW simulator
Ability to provide innovation and global vision throughout the company
Excellent communication, presentation and reporting skills
Experience working with highly technical teams and communicating to non-technical partners.
Excellent oral and written English.

Requirements:
BSC, MS or PHD in Electrical Engineering, Computer Engineering, or Computer Science.
Solid understanding of general purpose CPU micro-architecture, including load store unit, caches, cache coherence, memory hierarchy, multi-processor, multi-thread processor systems, memory technologies and memory controllers.
Ability to make trade-offs between power, performance and area to meet the requirements of the product.
Hand-on experience with high power-efficient CPU on chip interconnect, coherent fabric, memory controllers.
At least 8 years experience in architecture in one of the leading CPU companies
Experience modeling microprocessors using higher-level languages, like C/C++.
DESIRED
Co-operate and communicate well with the architecture and design teams.
Interact with the Product System architects, software teams and ASIC chip teams to define the overall architecture of the Processor ASIC including memory hierarchy.
Travel to Beijing and ShenZhen sites may be required.
Good presentation and internal customer interaction skills.

Requirements:
MS or PHD in Electrical Engineering, Computer Engineering, or Computer Science.
Minimum of 10 years of proven design experience in complex processor projects.
Familiarity with the ARM architecture and the micro-architecture for current ARM CPU cores.
Software development (C, assembly).
Experience modeling microprocessors using higher-level languages, like C/C++.
Excellent verbal and written communication skills.
Co-operate and communicate well with the architecture team and other members of development team.
Interact with the Product System architects, software teams and ASIC chip teams to define the overall architecture of the Processor ASIC including memory hierarchy.
Travel to US, Beijing and ShenZhen sites may be required.
Good presentation and internal customer interaction skills
MINIMAL REQUIREMENTS
Solid understanding of general purpose CPU micro-architecture, including knowledge of areas such as processor pipelines, load store unit, caches, cache coherence, memory hierarchy, multi-processor, multi-thread processor systems.
Ability to make trade-offs between power, performance and area appropriately to meet the requirements of the product.
Hand-on experience with high power-efficient CPU core successfully.
Understanding of CPU instruction set architecture and assembly language.
Ownership of the overall verification methodology for a CPU project.