דרושים » חשמל ואלקטרוניקה » Senior VLSI Architect

Requirements:
B.Sc. in Electrical/Computer Engineering or equivalent.
5+ years of experience as a VLSI Verification Engineer.
Expertise in System-Verilog and UVM.
Strong software development skills and the ability to develop reusable verification components and utilities.
Strong organizational and planning skills, with the ability to prioritize and drive verification projects to completion.
Effective communicator with a structured, detail-oriented approach to problem-solving and collaboration.
Advantages:
Experience with Git, Python, code templating methods, and open-source verification workflows.
Familiarity with full-chip level aspects of VLSI verification (reset architecture and sequences, power domains and modes, etc.).
Experience in firmware verification, including emulation-based verification on FPGA.
Experience with formal verification or mixed-signal simulation.

Requirements:
Minimum Skills And Experience
Experience with ASIC FE logic design. RTL coding, FE tools and signoff.
Experience in complex design (data-path or control-path)
Required Skills And Experience
BS/MS in Electrical and/or Computer Engineering with 8 to 10 years of experience.
Knowledge and experience in CPU or micro-controller designs (multi pipeline)
Processor system knowledge includes basic understanding of SoC systems as well as operating system software is a plus.
Great communication & teamwork skills.
Minimum Qualifications
Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field.
References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

Requirements:
BSc / MSc / PhD in Electrical Engineering, Computer Engineering, or a related field.
7+ years of experience in VLSI / ASIC design, chip architecture, or micro-architecture of complex blocks.
Strong background in high-speed networking systems such as:
o Ethernet Switches
o NPUs
o NICs
o Traffic Managers
o Fabric Switches
o High-performance processors
Skills
What Were Looking For
Excellent written and verbal communication skills in English.
Strong collaboration skills and the ability to work effectively across teams and disciplines.
Independent, self-driven, and capable of deep technical ownership.
Passion for innovation and cutting-edge technology.
Highly motivated with a proactive mindset.

Requirements:
Minimum Qualifications:
Knowledge and experience in high-speed interfaces, such as PCIe, Storage, Networking, Automotive interfaces
Several years of experience in ASIC design and development
Participation in standards organizations might be required by this position
Familiarity with VLSI and system-on-a-chip principles, operation, and internals
Preferred Qualifications:
Advantage to experience with ARM based SoC Real-time systems, SW architecture, and SW Drivers, Advantage to Linux and Android
Good communication skills across engineering disciplines, both verbally and in writing in Hebrew and English
Education Requirements Required:
Bachelor's, Electrical Engineering, or equivalent experience
Preferred: Master's, Electrical Engineering, or equivalent experience
Minimum Qualifications:
Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience.
OR
Master's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience.
OR
PhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.

Requirements:
BSc. in Electrical and/or Computer Engineering with up to 8 years of experience with RTL ASIC verification.
Knowledge and experience in one of the following: CPU, RISC-V architecture, micro-controllers, memory and cache controllers is an advantage.
Experience with Verilog, System Verilog
Experience with C/C++ (DPI-C).
Experience with SVA.
Experience with UVM methodology is an advantage.
Able to express complex concepts in fluent technical English.
Minimum Qualifications
Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 4+ years of Software Engineering, Hardware Engineering, Electrical Engineering, Systems Engineering, or related work experience.
OR
Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 3+ years of Software Engineering, Hardware Engineering, Electrical Engineering, Systems Engineering, or related work experience.
OR
PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field and 2+ years of Software Engineering, Hardware Engineering, Electrical Engineering, Systems Engineering, or related work experience.

Requirements:
BSC, MS or PHD in Electrical Engineering, Computer Engineering, or Computer Science.
Solid understanding of general purpose CPU micro-architecture, including load store unit, caches, cache coherence, memory hierarchy, multi-processor, multi-thread processor systems, memory technologies and memory controllers.
Ability to make trade-offs between power, performance and area to meet the requirements of the product.
Hand-on experience with high power-efficient CPU on chip interconnect, coherent fabric, memory controllers.
At least 8 years experience in architecture in one of the leading CPU companies
Experience modeling microprocessors using higher-level languages, like C/C++.
DESIRED
Co-operate and communicate well with the architecture and design teams.
Interact with the Product System architects, software teams and ASIC chip teams to define the overall architecture of the Processor ASIC including memory hierarchy.
Travel to Beijing and ShenZhen sites may be required.
Good presentation and internal customer interaction skills.

Requirements:
BSc. in Electrical and/or Computer Engineering with up to 12 years of experience with RTL ASIC verification, specializing in Formal verification.
Knowledge and experience in one of the following: CPU, RISC-V architecture, micro-controllers, memory and cache controllers is an advantage.
Experience with Verilog, System Verilog, SVA.
Able to express complex concepts in fluent technical English.
Minimum Qualifications
Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 4+ years of Software Engineering, Hardware Engineering, Electrical Engineering, Systems Engineering, or related work experience.
OR
Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 3+ years of Software Engineering, Hardware Engineering, Electrical Engineering, Systems Engineering, or related work experience.
OR
PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field and 2+ years of Software Engineering, Hardware Engineering, Electrical Engineering, Systems Engineering, or related work experience.

Requirements:
MS or PHD in Electrical Engineering, Computer Engineering, or Computer Science.
Minimum of 10 years of proven design experience in complex processor projects.
Familiarity with the ARM architecture and the micro-architecture for current ARM CPU cores.
Software development (C, assembly).
Experience modeling microprocessors using higher-level languages, like C/C++.
Excellent verbal and written communication skills.
Co-operate and communicate well with the architecture team and other members of development team.
Interact with the Product System architects, software teams and ASIC chip teams to define the overall architecture of the Processor ASIC including memory hierarchy.
Travel to US, Beijing and ShenZhen sites may be required.
Good presentation and internal customer interaction skills
MINIMAL REQUIREMENTS
Solid understanding of general purpose CPU micro-architecture, including knowledge of areas such as processor pipelines, load store unit, caches, cache coherence, memory hierarchy, multi-processor, multi-thread processor systems.
Ability to make trade-offs between power, performance and area appropriately to meet the requirements of the product.
Hand-on experience with high power-efficient CPU core successfully.
Understanding of CPU instruction set architecture and assembly language.
Ownership of the overall verification methodology for a CPU project.

Requirements:
3-5 years of hands-on experience with ASIC physical design (RTL-to-GDS).
Proven experience taking multiple full-chip SoCs from RTL through tapeout.
Deep knowledge of Cadence and/or Synopsys backend flows (experience with both is a strong plus).
Strong understanding of PnR, timing closure, SI, power, DRC/LVS, and signoff.
Excellent debugging and problem-solving skills.
Strong scripting skills in TCL and Python.
Nice-to-have / Advantage:
Experience with multiple power domains and low-power design techniques.
Background that spans both frontend (RTL) and backend.
Experience influencing or defining methodology across teams or projects.
Personal skills:
Innovation, quick learning abilities
Team player
Commitment ,full ownership of tasks
Excellent communication and presentation skills
Customer orientation
A strong sense of ownership.