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10/02/2026
משרה זו סומנה ע"י המעסיק כלא אקטואלית יותר
מיקום המשרה: יקנעם ותל אביב יפו
סוג משרה: משרה מלאה
משרות דומות שיכולות לעניין אותך
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
26/03/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part in flows development.
Requirements:
what we need to see:
b.sc./ m.sc. in electrical engineering/computer engineering or equivalent work experience.
5+ years of experience in physical design.
proven experience in rtl2gds flows and methodologies.
knowledge in physical design flows and methodologies (pnr, sta, physical verification).
deep understanding of all aspects of physical construction and integration.
strong background of physical design verification methodology lvs/drc.
familiarity with physical design eda tools (such as synopsys, cadence, etc).
great teammate.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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דיווח על תוכן לא הולם או מפלה
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שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
26/03/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part inflows development.
Requirements:
what we need to see:
b.sc./ m.sc. in electrical engineering/computer engineering or equivalent work experience.
3+ years of experience in physical design.
proven experience in rtl2gds flows and methodologies.
knowledge in physical design flows and methodologies (pnr, sta, physical verification).
deep understanding of all aspects of physical construction and integration.
knowledge in physical design verification methodology lvs/drc.
familiarity with physical design eda tools (such as synopsys, cadence, etc.).
great teammate.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8593770
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סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
26/03/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part in flows development.
Requirements:
what we need to see:
b.sc./ m.sc. in electrical engineering/computer engineering or equivalent work experience.
5+ years of experience in physical design.
proven experience in rtl2gds flows and methodologies.
knowledge in physical design flows and methodologies (pnr, sta, physical verification).
deep understanding of all aspects of physical construction and integration.
strong background of physical design verification methodology lvs/drc.
familiarity with physical design eda tools (such as synopsys, cadence, etc).
great teammate.
This position is open to all candidates.
 
Show more...
הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8593701
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סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
18/03/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.

Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.

Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.

Taking part inflows development.
Requirements:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent work experience.

Knowledge in physical design flows and methodologies (PNR, STA, physical verification).

Deep understanding of all aspects of Physical construction and Integration.

Knowledge in Physical Design Verification methodology LVS/DRC.

Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).

Great teammate.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8583558
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סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
26/03/2026
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
we are looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of exciting designs. resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part in flow development.
Requirements:
what we need to see:
b.sc./ m.sc. in electrical engineering/computer engineering or equivalent experience.
knowledge in physical design flows and methodologies (pnr, sta, physical verification).
deep understanding of all aspects of physical construction and integration.
knowledge in physical design verification methodology lvs/drc.
familiarity with physical design eda tools (such as synopsys, cadence, etc.).
2-3 years of relevant experience
great teammate.
our company has some of the most forward-thinking people in the world working for us. are you a creative and autonomous engineer who loves a challenge? are you ready to become the engineer you always wanted to be? come and be part of the best physical design team in the industry!
This position is open to all candidates.
 
Show more...
הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8593334
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סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
26/03/2026
Location: Yokne`am
Job Type: Full Time
looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part inflows development.
Requirements:
what we need to see:
b.sc./ m.sc. in electrical engineering/computer engineering or equivalent experience.
2+ years of experience.
proven experience in rtl2gds flows and methodologies. (advantage)
knowledge in physical design flows and methodologies (pnr, sta, physical verification). (advantage)
deep understanding of all aspects of physical construction and integration.
familiarity with physical design eda tools (such as synopsys, cadence, etc.).
great teammate.
nvidia has some of the most forward-thinking people in the world working for us. are you a creative and autonomous engineer who loves a challenge? are you ready to become the engineer you always wanted to be? come and be part of the best physical design team in the industry!
This position is open to all candidates.
 
Show more...
הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8593525
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סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
26/03/2026
Location: Yokne`am
Job Type: Full Time
we are looking for best-in-class physical design power engineer to join our outstanding networking silicon power engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput, lowest latency and best power! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you will be doing:
power optimization of physical design, of blocks/top-level/fc under challenging constraints.
optimization involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise fixes.
power estimation and power modeling.
Requirements:
what we need to see:
b.sc./ m.sc. or equivalent experience in electrical engineering/computer engineering.
2+ years of experience in physical design and/or be power optimization aspects.
familiarity with physical design eda tools (such as synopsys, cadence, etc.).
knowledge in physical design flows and methodologies (pnr, sta, physical verification) is an advantage.
fe design experience is an advantage.
excellent problem-solving, partnership, and interpersonal skills.
our company has some of the most forward-thinking people in the world working for us. are you a creative and autonomous engineer who loves a challenge? are you ready to become the engineer you always wanted to be? come and be part of the best physical design team in the industry!
This position is open to all candidates.
 
Show more...
הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8593398
סגור
שירות זה פתוח ללקוחות VIP בלבד
סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
27/03/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part in flows development.
Requirements:
what we need to see:
b.sc./ m.sc. in electrical engineering/computer engineering or equivalent work experience.
5+ years of experience in physical design.
proven experience in rtl2gds flows and methodologies.
knowledge in physical design flows and methodologies (pnr, sta, physical verification).
deep understanding of all aspects of physical construction and integration.
strong background of physical design verification methodology lvs/drc.
familiarity with physical design eda tools (such as synopsys, cadence, etc).
great teammate.
This position is open to all candidates.
 
Show more...
הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8594052
סגור
שירות זה פתוח ללקוחות VIP בלבד
סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
22/03/2026
חברה חסויה
Location: More than one
Job Type: Full Time
We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:
You will be responsible for complex physical design unit designs, ensuring integration within our innovative builds.
We expect you to run, debug, and approve PnR and verification flows across multiple projects, ensuring strict adherence to our high standards.
You will perform physical design implementation, planning and optimization, contributing to the development of our groundbreaking chips.
Requirements:
What we need to see:
B.SC./ M.SC. in Electrical Engineering
You should have at least 5+ years of hands-on Physical Design 'Place and Route' experience, demonstrating your proven expertise.
A strong background in Physical Design methodology, including Synthesis, Floorplan, CTS and Routing, is necessary.
Sign-off stages experince such as , 'STA', 'PV', 'LEC' and 'EMIR'.
In-depth knowledge of advanced silicon process technologies.
Familiarity with physical build EDA tools, including Synopsys and Cadence.
A great teammate who thrives in a collaborative environment.
AI tools orientation or alternatively a desire to learn.

Ways to stand out from the crowd:
AI prompting experience.
Experience in Linux environments.
TCL, Python, shell scripting abilities.
Experience with data collection and analysis.
Understanding of the chip and die verification process.
This position is open to all candidates.
 
Show more...
הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8586970
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סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
26/03/2026
Location: Yokne`am
Job Type: Full Time
we are looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
you will be responsible for chip floorplan and pin placement, ensuring integration within our innovative builds.
we expect you to run, debug, and approve physical verification flows across multiple projects, ensuring strict adherence to our high standards.
you will perform physical layout implementation, planning and optimization, contributing to the development of our groundbreaking chips.
we are widely considered to be one of the technology worlds most desirable employers. we have some of the most forward-thinking people in the world working for us. are you a creative and autonomous engineer who loves a challenge? are you ready to become the engineer you always wanted to be? come and be part of the best physical design team in the industry!
Requirements:
b.sc./ m.sc. in electrical engineering
you should have at least 5+ years of hands-on layout experience, demonstrating your proven expertise.
a strong background in physical verification methodology, including erc, lvs and drc, is necessary.
in-depth knowledge of advanced silicon process technologies.
familiarity with physical build eda tools, including synopsys and cadence.
a great teammate who thrives in a collaborative environment.
ai tools orientation or alternatively a desire to learn.
ways to stand out from the crowd:
experience in Linux environments.
tcl, Python, shell scripting abilities.
experience with data collection and analysis
understanding of the chip and die verification process
This position is open to all candidates.
 
Show more...
הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8593216
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