דרושים » חשמל ואלקטרוניקה » senior physical design backend engineer

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לפני 20 שעות
Location: Tel Aviv-Yafo
Job Type: Full Time
looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part in flows development.
Requirements:
what we need to see:
b.sc./ m.sc. in electrical engineering/computer engineering or equivalent work experience.
5+ years of experience in physical design.
proven experience in rtl2gds flows and methodologies.
knowledge in physical design flows and methodologies (pnr, sta, physical verification).
deep understanding of all aspects of physical construction and integration.
strong background of physical design verification methodology lvs/drc.
familiarity with physical design eda tools (such as synopsys, cadence, etc).
great teammate.
This position is open to all candidates.
 
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לפני 20 שעות
Location: Tel Aviv-Yafo
Job Type: Full Time
looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part in flows development.
Requirements:
what we need to see:
b.sc./ m.sc. in electrical engineering/computer engineering or equivalent work experience.
5+ years of experience in physical design.
proven experience in rtl2gds flows and methodologies.
knowledge in physical design flows and methodologies (pnr, sta, physical verification).
deep understanding of all aspects of physical construction and integration.
strong background of physical design verification methodology lvs/drc.
familiarity with physical design eda tools (such as synopsys, cadence, etc).
great teammate.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
לפני 19 שעות
Location: Tel Aviv-Yafo
Job Type: Full Time
looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part inflows development.
Requirements:
what we need to see:
b.sc./ m.sc. in electrical engineering/computer engineering or equivalent work experience.
3+ years of experience in physical design.
proven experience in rtl2gds flows and methodologies.
knowledge in physical design flows and methodologies (pnr, sta, physical verification).
deep understanding of all aspects of physical construction and integration.
knowledge in physical design verification methodology lvs/drc.
familiarity with physical design eda tools (such as synopsys, cadence, etc.).
great teammate.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
18/03/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.

Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.

Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.

Taking part inflows development.
Requirements:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent work experience.

Knowledge in physical design flows and methodologies (PNR, STA, physical verification).

Deep understanding of all aspects of Physical construction and Integration.

Knowledge in Physical Design Verification methodology LVS/DRC.

Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).

Great teammate.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8583558
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דיווח על תוכן לא הולם או מפלה
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סגור
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
לפני 22 שעות
Location: Tel Aviv-Yafo
Job Type: Full Time
we are looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part inflows development.
Requirements:
what we need to see:
b.sc./ m.sc. in electrical engineering/computer engineering or equivalent work experience.
knowledge in physical design flows and methodologies (pnr, sta, physical verification).
deep understanding of all aspects of physical construction and integration.
knowledge in physical design verification methodology lvs/drc.
familiarity with physical design eda tools (such as synopsys, cadence, etc.).
great teammate.
our company has some of the most forward-thinking people in the world working for us. are you a creative and autonomous engineer who loves a challenge? are you ready to become the engineer you always wanted to be? come and be part of the best physical design team in the industry!
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8593446
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
לפני 22 שעות
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
we are looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of exciting designs. resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part in flow development.
Requirements:
what we need to see:
b.sc./ m.sc. in electrical engineering/computer engineering or equivalent experience.
knowledge in physical design flows and methodologies (pnr, sta, physical verification).
deep understanding of all aspects of physical construction and integration.
knowledge in physical design verification methodology lvs/drc.
familiarity with physical design eda tools (such as synopsys, cadence, etc.).
2-3 years of relevant experience
great teammate.
our company has some of the most forward-thinking people in the world working for us. are you a creative and autonomous engineer who loves a challenge? are you ready to become the engineer you always wanted to be? come and be part of the best physical design team in the industry!
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
לפני 4 שעות
Location: Tel Aviv-Yafo
Job Type: Full Time
physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part in flows development.
Requirements:
what we need to see:
b.sc./ m.sc. in electrical engineering/computer engineering or equivalent work experience.
5+ years of experience in physical design.
proven experience in rtl2gds flows and methodologies.
knowledge in physical design flows and methodologies (pnr, sta, physical verification).
deep understanding of all aspects of physical construction and integration.
strong background of physical design verification methodology lvs/drc.
familiarity with physical design eda tools (such as synopsys, cadence, etc).
great teammate.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8594052
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
לפני 22 שעות
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
we are looking for best-in-class sta physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you will be doing:
sta analysis of blocks/top-level according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of static timing analysis - constraints, environment, models generation and timing eco generation for block level and full chip level.
taking part inflows development.
Requirements:
what we need to see:
b.sc. in electrical engineering/computer engineering.
2-3 years of experience as sta engineer.
ability to quickly adapt to new technology and go deep into new areas
strong communication skills
great teammate.
drive new solutions based on any issues that arise
ways to stand out from the crowd:
knowledge in physical design flows and methodologies (pnr, sta, physical verification).
familiarity with physical design eda tools (such as synopsys, cadence, etc.).
our company has some of the most forward-thinking people in the world working for us. are you a creative and autonomous engineer who loves a challenge? are you ready to become the engineer you always wanted to be? come and be part of the best physical design team in the industry!
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8593313
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
4 ימים
חברה חסויה
Location: More than one
Job Type: Full Time
We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:
You will be responsible for complex physical design unit designs, ensuring integration within our innovative builds.
We expect you to run, debug, and approve PnR and verification flows across multiple projects, ensuring strict adherence to our high standards.
You will perform physical design implementation, planning and optimization, contributing to the development of our groundbreaking chips.
Requirements:
What we need to see:
B.SC./ M.SC. in Electrical Engineering
You should have at least 5+ years of hands-on Physical Design 'Place and Route' experience, demonstrating your proven expertise.
A strong background in Physical Design methodology, including Synthesis, Floorplan, CTS and Routing, is necessary.
Sign-off stages experince such as , 'STA', 'PV', 'LEC' and 'EMIR'.
In-depth knowledge of advanced silicon process technologies.
Familiarity with physical build EDA tools, including Synopsys and Cadence.
A great teammate who thrives in a collaborative environment.
AI tools orientation or alternatively a desire to learn.

Ways to stand out from the crowd:
AI prompting experience.
Experience in Linux environments.
TCL, Python, shell scripting abilities.
Experience with data collection and analysis.
Understanding of the chip and die verification process.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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סגור
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
לפני 21 שעות
Location: Tel Aviv-Yafo
Job Type: Full Time
looking for outstanding chip design Verification engineers to join our networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
come and take a significant part in designing and verifying our ground-breaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.
what you will be doing:
work in a combined design and verification team which develops core units within the networking silicon.
build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.
work closely with multiple teams within organizations such as architecture, micro- architecture, full-chip, fw and post-silicon validation.
your daily work will involve all aspects of design verification: planning, coding, coverage and integration
Requirements:
what we need to see:
b.sc or above in electrical engineering or computer engineering, graduation with high scores.
5+ years of validated experience in chip design dynamic verification.
professional verification experience, knowledge in advanced verification methodologies and tools.
demonstrates deep understanding in design and verification logic.
strong debugging, problem-solving and analytical skills.
a great teammate with strong communication and interpersonal skills.
self-motivated, ability to work independently and drive tasks to completion.
ways to stand out from the crowd:
experience in developing verification environments in Specman.
prior design or verification experience of high-speed interconnects and/or SOC.
knowledge in network flows and protocols.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8593560
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
חברה חסויה
Location: Tel Aviv-Yafo and Caesarea
Job Type: Full Time and Hybrid work
We are seeking a CAD Engineer to join the Physical Design team.

You'll be joining our Physical Design team within us, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You will be the tech lead for CAD within the team, leveraging your extensive backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.
Requirements:
Minimum Qualifications:
A VLSI Design Engineer with extensive experience in backend design.
B.Sc./M.Sc. in Electrical Engineering or Computer Engineering with relevent background.
5+ years of hands-on experience in a relevant domain.
Strong understanding of Place & Route flow.

Preferred Qualifications:
Deep understanding of Physical construction and Integration.
Knowledge of Physical Design Verification methods like LVS/DRC and formal verification.
Experience with PD CAD and Physical Design EDA tools (e.g., Synopsys, Cadence).
Ability to support technology adoption and new tool integration.
Great teammate, self-learner, and able to work independently.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8546220
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