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We are looking for a talented Signal Processing and Communications Engineer to bridge the gap between simulation and real-world performance for high-speed wireline communication links. In this role, you will analyze lab results to refine development simulators and align them closely with actual SerDes performance, ensuring future designs are driven by real measurements, not just theoretical models. You will play a critical role in optimizing current designs for faster, more reliable chip bring-up and shaping the architecture of next-generation solutions. As part of the algorithm team, you will be actively involved in debugging unique and complex phenomena observed in the lab, working alongside post-silicon engineers to directly influence product performance. Separately, this role also provides a rare opportunity to gain broad system-level understanding, offering visibility into how the SerDes integrates and interacts within the larger chip architectureinsight typically beyond the standard algorithmic scope.

You will collaborate closely with analog and digital designers, signal integrity experts, and other cross-functional teams to ensure simulation models and lab results accurately represent real-world system behavior. If you are passionate about solving complex signal processing challenges and working at the forefront of technology, we want to hear from you.

What you will be doing:

Develop HW tools and flows to improve lab debuggability and visibility.

Correlate simulation results with lab measurements to improve model accuracy.

Work closely with cross-disciplinary teams to ensure accurate and reliable model representation.

Find performance bottlenecks

Characterize and evaluate analog and digital blocks in the lab to contribute to the DSP architecture and modeling strategies for next-generation SerDes designs.