דרושים » הנדסה » Senior IC Test Engineer

Collaborate with Architecture, Design and Verification teams to develop new product bring-up, validation, characterization, qualification strategies and manufacturing test solutions for new High Performance Computing (HPC) products in advanced process technologies.
Verify test solutions on pre-silicon models (simulation or emulation) and develop ATE test modules, DC tests, binning, production and characterization flows.
Develop and validate test programs on Automated Test Equipment (ATE) platforms for new product integration (NPI) in preparation for high volume manufacturing (HVM), working with ATE vendors.
Support product, volume data analysis of screening and characterization data, test time and yield improvements, assess test escapees and Return Materials/Merchandise Authorizations (RMAs), localize failures, implement containment measures and partner with design, manufacturing, quality and reliability teams to root cause and implement corrective actions.
Develop tools, flows and methodologies to improve and automate the testing.

Execute activities in the design, implementation, and verification of Design for Testing solutions for Application-Specific Integrated Circuit (ASICs).
Develop DFT strategy for hierarchical DFT, Scan, and Automatic Test Pattern Generation (ATPG).
Perform ATPG scan, cover debug and motivate design fixes for coverage and quality improvements.
Perform scan verification at Register-Transfer Level (RTL) and gate level.
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT Scan requirements are met and mutual dependencies are managed.

our team is responsible to foster quality and excellence in our company's products and processes across the entire company. MEQ focuses on ensuring high customers' satisfaction through continuous improvement and implementation of automotive standards and best-practices such as ASPICE, IATF16949, ISO 9001, VDA/AIAG Core Tools and ISO26262, both internal and across the entire supply chain, In order to support MEQ objectives, The QMS & Production Quality team is looking for a Production Quality & Reliability Engineer
What will your job look like:
Define and implement Quality & Reliability (QnR) framework and workplan for our company's components from first Silicon and onwards (from scratch)
Define and lead/participate in: QnR validation activities, Fault Isolation, Failure analysis according to 8D method, Yield enhancement, SORT kill criteria definition based on reliability risks, Statistical bin limits.
Work closely with colleagues from other departments (PMs, development engineers, production engineers, management) and other organizations (suppliers and customers).
Work with contract manufacturers to analyze the production process, process capability and capacity and measurement systems capability.
Assess and control the activities through performing VDA6.3 audits.
Create, manage and update PPAP folders for components.
Identify opportunities for improvement and execute them.
Create relevant work items templates and coach the teams how to use them.
Assess KPIs of processes and activities and suggest corrective actions and improvement.
Represent components QnR related issues with customers, suppliers and 3rd party organizations.

Create software solutions that improve the hardware post-silicon testing process through automation. This includes, but is not limited to, developing and maintaining an ATE program development infrastructure for both production and development environments.
Propose, design and implement software automation that directly addresses bottlenecks in today's post-silicon test flow, from DFT to ATE.
Work directly with a Hardware team on projects - prototype and then deploy tools to make a positive impact on Google's chip hardware development process.
Participate in, or lead design reviews with peers and stakeholders to decide amongst available technologies.
Review code developed by other developers and provide feedback to ensure best practices (e.g., style guidelines, checking code in, accuracy, testability, and efficiency).

Develop and implement strategies for high volume manufacturing of SoC products, including troubleshooting, ATE test coverage optimization, DPPM reduction, Test cost reduction, power and performance assurance, and product data integration and correlation between system, ATE, and System Level Test (SLT).
Drive interactions with wafer fabs and OSATs, own and drive checkpoints for key quality metrics.
Drive volume ramp and mass production through test program releases, volume data analytics, lot disposition, extended test time reduction, yield improvement, and RMA handling.
Collaborate with cross-functional teams across the globe including ATE and SLT Test Engineering, Q&R, Packaging, Supplier Management and Operations to build, deploy, and maintain a high volume manufacturing screening solution.
Support setup and maintenance of test, diagnosis, and yield analysis infrastructure, including RMA support.

As a Technical Program Manager for Silicon Development, you will use your technical and management experience to lead the development and execution of complex, multidisciplinary SoC projects. You will plan programs and manage their execution from early concepts through development to tape-out and production. You will collaborate closely with architecture, design, verification, physical implementation and manufacturing teams throughout the SoC execution life cycle. This includes making technical decisions for the chip designs and methodology, driving project schedules, identifying risks and communicating them to all stakeholders, and managing partner teams.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of platforms, we make product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities
Plan, coordinate, and deliver custom silicon products.
Assess complexity and scope out the project, generate task lists, build a project timeline and work with the teams to make it into reality.
Lead the data-driven schedules and milestones, track the progress, proactively identify potential future issues, and identify mitigations with the team leaders.
Drive technical, budgetary, and schedule trade-off discussions with cross-functional teams.
Manage project execution and issues through design, development, test, manufacturing, deployment and sustaining activities for silicon and hardware products.

Develop DFT strategy and architecture (e.g., hierarchical DFT, Memory Built-In Self Test (MBIST), ATPG).
Complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high-test quality.
Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks.
Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces.
Document DFT architecture, test sequences, and boot-up sequences associated with test pins.

our company, a world leader in driver assistant systems and autonomous vehicles, is looking for silicon validation Tech Lead engineer for the range of its next generation SoCs supporting its radar systems.
Our team is responsible for validating our company's radar SoCs, utilizing Pre-Silicon environments, as well as Post-Silicon platforms.
We are developing fully embedded C++ based validation environment for our needs.
You will be taking part in developing anything from environment and drivers through system modules such as file system, network stack, memory management and more, and up to complex automation tools in both C++ and python.
What will your job look like
Get a deep understanding of our chip hardware IP blocks, both analog and digital.
Develop our validation environment.
Develop, port, or add features to the product drivers using Technical Specs and existing modules.
Define, develop and execute various complex validation scenarios on the SoC.
Debug complex SoC problems using embedded GDB, JTAG probes, going down to signal level using scopes.
Take part in Next Gen SoC's Power-On's and platforms Bring-Up's.
Collaborate with other SW/Embedded and HW/Electrical Validation teams across the company.

A Senior Security Engineer is expected to be proficient in multiple domains. This is a leadership role within the Annapurna security team and you will be sought out for advice on technical and business issues. Efficient time management skills are required along with the ability to deliver results in the face of uncertainty. A Senior Security Engineer will proactively share knowledge across the community and will be a key company resource in one or more of the core areas of security. He will lead security reviews of large projects while setting standards and defining best practices for our Security teams.

Engineers in this role must show exemplary judgment in making technical trade-offs between short versus long term security and business goals. They must also demonstrate resilience and navigate difficult situations with composure and tact. A broad understanding of the business and its interconnections is required. This position will also provide training, advice, and mentorship to other engineers throughout us.

we are looking for an Embedded SW Engineer for SystemC Modeling that include Performance and Program view Modeling. You will be part of VLSI emulation team , working on current and next-generation designs for next generation sensors.
The SystemC models are fundamental parts of the VLSI chip infrastructure, they are used during HW architecture definition phase and by SW developers for system shift left.
What will your job look like:
You will work on Critical performance analysis and optimizations on the ASIC micro architecture as multi-NOC , DDR and CPU .
You will work on developing SystemC models that describe the RTL models on High level language and enable true system . level shift left for the embedded SW team.
You will have the opportunity to work on state-of-the-art simulation and profiling tools and adopt them to our company's needs.
You will work closely with HW architects and SW/Algorithms developers.