דרושים » הנדסה » SoC DFT Engineer, Google Cloud

Requirements:
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
2 years of experience in Automatic Test Pattern Generation (ATPG) methods.
Experience with multiple projects in Design for Testing (DFT) scan design and verification.
Experience with Design for Testing (DFT) techniques and tools, Application-Specific Integrated Circuit (ASIC) Design for Testing synthesis, simulation, and verification flow.

Preferred qualifications:
Master's degree in Electrical Engineering.
Experience working with Automated Test Equipment (ATE) engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, debug of silicon issues).
Experience in System on a chip (SoC) cycles, including silicon bringup and silicon debug activities.
Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and Memory Built-In Self Test (MBIST)).
Experience in fault modeling.

Requirements:
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
8 years of experience in Automatic Test Pattern Generation (ATPG) methods.
4 years of people management experience developing employees.
Experience with multiple projects in DFT design and verification, DFT specification, definition, architecture, and insertion.
Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow.
Experience in leading DFT activities throughout an ASIC development flow.

Preferred qualifications:
Master's degree in Electrical Engineering or a related field.
Experience in JTAG and iJTAG protocols and architectures.
Experience in post-silicon test or product engineering.
Experience in SoC cycles, silicon bring-up, and silicon debug activities.
Knowledge of fault modeling techniques.

Requirements:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
2 years of experience in design, test, manufacturing, or process engineering.
Experience with Application-Specific Integrated Circuit (ASIC) test methodologies (mbist, atpg, dft serdes, sensors).
Experience coding in Python, Java, C# or C/C++ and Advantest or Teradyne ATE platforms.
Experience in pre-silicon validation, test content generation, ATE program development, and post-silicon enabling from New Product Introduction through High Volume Manufacturing.

Preferred qualifications:
Experience in developing or integrating Manufacturing Test Hardware using Electrical and Thermo-mechanical components.
Experience in creating Manufacturing Test strategies for Printed Circuit Board Assembly (PCBA) and systems that cover Structural through Functional and System tests.
Experience in ATE hardware design and proliferation: loadboards/probecards, handler kits, sockets, and thermal control solutions.
Experience in developing automations for pre-silicon verification and post-silicon test-generation/test-program domains.
Experience with CPU/GPU SoC architecture, design, validation and debug.

Requirements:
Bachelor's degree or equivalent practical experience.
5 years of industry experience with systems and debugging.
5 years of experience in ATE tools, flows, and methodologies.
Experience in ATE test development, from DFT/Design Verification (DV) to ATE (e.g., Reset, Automatic Test Pattern Generation (ATPG), Memory Built-In Self Test (MBIST), or functional content development to ATE patterns).
Experience in ATE test method library development - taking ATE low level drivers and developing automated solutions.

Preferred qualifications:
Proficiency in code and system health, diagnosis and resolution, and software test engineering.
Understanding of object oriented programming and functional programming.
Excellent software skills and design practices

Requirements:
Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
Experience in full VLSI design cycle.
Experience in RTL implementation of low power designs.
Experience in VLSI development with Verilog, SystemVerilog, System Verilog Assertions (SVA), or VHDL, and with design verification, synthesis, timing/power analysis, and DFT.

Preferred qualifications:
Experience in four or more SoC cycles.
Knowledge of modern high-performance CPU architecture and micro-architecture.

Requirements:
Bachelor's degree in Electrical Engineering, Computer Engineering, a related field, or equivalent practical experience.
Experience with design from micro-architecture through implementation with Verilog/SystemVerilog, or VHDL language.
Scripting experience.

Preferred qualifications:
Experience with ASIC design methodologies for front quality checks (e.g., Lint, CDC/RDC, Synthesis, design for testing, ATPG/Memory BIST, UPF, and Low Power Optimization/Estimation).
Experience with chip design flow, physical design, IP integration, and Design for Testing (DFT).
Ability to muti-task, and have a can-do approach.
Excellent communication and facilitation skills.

Requirements:
Bachelor's degree in BSC, or a related field, or equivalent practical experience.
10 years of experience architecting networking ASICs from specification to production.
Experience working with design networking like: RDMA and or packet processing and system design principles for low latency, high throughput, security, and reliability.
Experience developing RTL for ASIC subsystems.
Experience in Cross-functional, micro-architecture, design, verification, logic synthesis, and timing closure.

Preferred qualifications:
Experience working with software teams optimizing the hardware/software interface.
Experience architecting networking switches, end points, and hardware offloads.
Experience in Transmission Control Protocol (TCP), IP, Ethernet, PCIE and Dynamic random-access memory (DRAM), Network on Chip (NoC) principles and protocols.
Experience in a procedural programming language (e.g. C++, Python, Go.).
Experience in estimating performance by analysis, modeling, and network simulation. Skilled in defining and driving performance test plans.
Understanding of packet classification, processing, queueing, scheduling, switching, routing, traffic conditioning, and telemetry.

Requirements:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
Experience working with design networking like Remote Direct Memory Access (RDMA) or packet processing and system design principles for low latency, high throughput, security, and reliability.
Experience in creating and using verification components and environments in standard verification methodology.

Preferred qualifications:
Experience in verifying digital systems using standard Internet Protocol (IP) components or interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
Experience in Transmission Control Protocol (TCP), IP, Ethernet, PCIE and Dynamic random-access memory (DRAM), Network on Chip (NoC) principles and protocols.
Experience in estimating performance by analysis, modeling, and network simulation in defining and driving performance test plans.
Experience with verification techniques, and the full verification life cycle.
Experience with performance verification of ASICs and ASIC components.
Experience with ASIC standard interfaces and memory system architecture.

Requirements:
Bachelor's degree or equivalent practical experience.
8 years of experience architecting networking ASICs from specification to production.
Experience working with design networking like: RDMA and or packet processing and system design principles for low latency, high throughput, security, and reliability.
Experience developing Register Transfer Level (RTL) for ASIC subsystems.
Experience in Cross-functional, micro-architecture, design, verification, logic synthesis, and timing closure.

Preferred qualifications:
Experience in Transmission Control Protocol (TCP), IP, Ethernet, PCIE and Dynamic random-access memory (DRAM), Network on Chip (NoC) principles and protocols.
Experience in estimating performance by analysis, modeling, and network simulation. Skilled in defining and driving performance test plans.
Experience working with software teams optimizing the hardware/software interface.
Experience architecting networking switches, end points, and hardware offloads.
Experience in a procedural programming language (e.g. C++, Python, Go.).
Understanding of packet classification, processing, queueing, scheduling, switching, routing, traffic conditioning, and telemetry.

Requirements:
Bachelor's degree or equivalent practical experience.
8 years of experience architecting networking ASICs from specification to production.
Experience working with design networking such as RDMA or packet processing and system design principles for low latency, high throughput, security, and reliability.
Experience developing RTL for ASIC subsystems.
Experience in Cross-functional, micro-architecture, design, verification, logic synthesis, and timing closure.

Preferred qualifications:
Experience in Transmission Control Protocol (TCP), IP, Ethernet, PCIE and Dynamic random-access memory (DRAM), Network on Chip (NoC) principles and protocols.
Experience working with software teams optimizing the hardware/software interface.
Experience architecting networking switches, end points, and hardware offloads.
Experience in a procedural programming language (e.g., C++, Python, Go).
Experience in estimating performance by analysis, modeling, and network simulation. Skilled in defining and driving performance test plans.
Understanding of packet classification, processing, queueing, scheduling, switching, routing, traffic conditioning, and telemetry.