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The Chip Test Engineer plays a crucial role in designing, developing, and implementing automated test for IC chips and systems for Automotive industry. The Test Engineer is responsible to define and develop tests, design test features, program test scripts, and analyze test results to ensure the quality and functionality of products. The Test Engineer collaborates with cross-functional teams to troubleshoot issues, improve test processes, and support product development efforts.

Responsibilities:
Develop and implement test strategies, plans, and procedures for ATE systems to ensure comprehensive testing of ICs.
Design and develop test features, test programs, and test scripts for automated test environment (ATE) based on product specifications and requirements.
Collaborate with design engineers, product manager, production vendors and manufacturing teams to understand product functionality, performance requirements, and testability considerations.
Conduct feasibility studies and risk assessments to identify potential challenges and develop mitigation strategies for test development and implementation.
Develop test program based on code languages C++ , Java and Python.
Debug, troubleshoot, and resolve issues with ATE hardware, software, and test scripts to ensure reliable and accurate test results.
Analyze test data and results to identify trends, anomalies, and potential defects, and provide feedback to design and development teams for product improvement.
Develop and maintain documentation for test procedures, specifications, and configurations.
Collaborate with vendors and suppliers to evaluate and select ATE equipment, components, and software tools that meet project requirements and performance standards.
Stay abreast of industry trends, advancements in test technologies, and best practices in automated testing to drive continuous improvement in test processes and methodologies.

As a Tech Leader in the AI Algorithm Engineering group, you will play a pivotal role in both managing end-to-end AI research and development efforts and hands-on involvement in key-initiatives. Your responsibility will include design, implementation, guidance and mentoring for team members, and representing the AI considerations in cross-team discussions. You will leverage your extensive experience to lead multiple AI projects, and will be a key figure in leading successful execution and in finding creative solutions to difficult bottlenecks, across data, AI, engineering and product considerations.
Responsibilities:
Lead the design, development, and implementation of accurate and robust AI algorithms for medical data with a hands-on approach.
Collaborate with cross-functional teams, including data scientists, software engineers, product managers and clinical data experts, to ensure AI considerations have a profound impact on R&D and Product decisions across the projects.
Design and conduct research and experimentation to improve algorithm performance and accuracy.
Stay at the forefront of the latest advancements in AI and machine learning, particularly in the medical domain, and drive their adoption within the team.
Oversee multiple projects, ensuring successful execution, timely delivery and alignment with product and business objectives.
Provide strategic direction and technical mentoring to elevate the capabilities of the AI team.

As BSP / Embedded Team Leader, you will lead a team of talented embedded software engineers responsible for the development, maintenance, and optimization of Board Support Packages for our custom hardware platforms. You will work closely with hardware, kernel, and system software teams to ensure robust and efficient low-level software integration.

Responsibilities:
Lead the BSP / Embedded development team, providing technical direction, mentorship, and guidance.
Design, develop, and maintain BSP components including bootloaders, device drivers, and board initialization code.
Collaborate with hardware teams to bring up new boards and support silicon validation.
Ensure seamless integration of BSP with Linux (or other OS) kernels and embedded software stacks.
Define and enforce coding standards, development processes, and quality benchmarks.
Own the delivery of BSP milestones in alignment with project timelines.
Troubleshoot and resolve low-level system issues and performance bottlenecks.
Stay up-to-date with industry trends, tools, and best practices in embedded systems.

The Project Manager is ultimately responsible for project oversight and review of all disciplines including electrical, mechanical, controls, and architectural. A fundamental understanding of these systems is required, as the individual will be expected to identify areas for improvement as well as act on data provided from other teams and organizations. Ideal candidates will possess the ability identify and deploy innovative solutions to address operational challenges. This role requires both independent contribution as well as the ability to work across stakeholder teams. The scope of projects will include but not limited to the improvement of electrical, mechanical, fire detection and building automation systems. The Project Manager is responsible for the overall direction, coordination, implementation, control and completion of specific projects ensuring consistency with company strategy, commitments and goals.

If you are passionate about the customer experience and you want to contribute to the operational excellence of data centers then this may be the challenge youve been looking for!

Key job responsibilities
- Project management and oversight of construction related activities as they relate to modifying existing infrastructure for the purpose of installing new or to replace end of life equipment. This will include the ownership of the project scope, timeline, and budget.
- Provide project management for specific initiatives aimed at increasing the resiliency of our data centers.
- Electrical design and review of designs associated with the optimization of existing data centers.
- Construction/project package drawing review.
- Creation of project scope, request for proposals, and capital requests.
- Total project quality including the creation of a commissioning plan and oversight of the execution.
- Recording and reporting key metrics to team members and management.
- Operational support including review of procedures, best practices, and maintenance initiatives.
- Drive teams to perform troubleshooting and root cause failure analysis associated with equipment or electrical failures.
- Work with contractors and vendors to deliver efficient and high quality project turnovers.
- Be a leader within the group as well as within internal and external teams that support the data center.
- Travel to support projects in the EMEA region

Lead and execute activities in the design, implementation, and verification of DFT solutions for large-scale ASICs.
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage the DFT team's workload and deliverables, provide technical leadership and guidance to the team.
Lead DFT execution of a silicon project - planning, execution, tracking, quality, and signoff.

As a Technical Program Manager for Silicon Development, you will use your technical and management experience to lead the development and execution of complex, multidisciplinary SoC projects. You will plan programs and manage their execution from early concepts through development to tape-out and production. You will collaborate closely with architecture, design, verification, physical implementation and manufacturing teams throughout the SoC execution life cycle. This includes making technical decisions for the chip designs and methodology, driving project schedules, identifying risks and communicating them to all stakeholders, and managing partner teams.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of platforms, we make product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities
Plan, coordinate, and deliver custom silicon products.
Assess complexity and scope out the project, generate task lists, build a project timeline and work with the teams to make it into reality.
Lead the data-driven schedules and milestones, track the progress, proactively identify potential future issues, and identify mitigations with the team leaders.
Drive technical, budgetary, and schedule trade-off discussions with cross-functional teams.
Manage project execution and issues through design, development, test, manufacturing, deployment and sustaining activities for silicon and hardware products.

We are seeking a highly motivated Chip Design Architect to join our team of experts and help shape the future of high-performance computing. Our next-generation Infiniband and NVL switches will be at the forefront of connecting and powering the world's most advanced compute clusters, from supercomputers used in AI research to high-performance clusters used in industries such as finance and research labs. As a Chip Design Architect at our company, you will have the opportunity to work on some of the most cutting-edge technology and help to drive the innovation of our next generation of switches that will be used by top researchers and engineers around the world. The products you'll develop will be integrated in many leading-edge compute clusters, and supercomputers, and you'll be part of a team with a strong track record of success.

What you will be doing:

Collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and hardware teams, to ensure the successful execution of the project.

Define the HW boot, clock and Reset architecture for Switch ASIC.

Develop slow-speed interface architecture specifications and design guidelines, conduct trade-off analysis for different architecture options, and oversee the implementation of the chosen architecture by the chip design / FW / SW teams.

Execute activities in the design, implementation, and verification of Design for Testing solutions for Application-Specific Integrated Circuit (ASICs).
Develop DFT strategy for hierarchical DFT, Scan, and Automatic Test Pattern Generation (ATPG).
Perform ATPG scan, cover debug and motivate design fixes for coverage and quality improvements.
Perform scan verification at Register-Transfer Level (RTL) and gate level.
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT Scan requirements are met and mutual dependencies are managed.

Define and lead qualification hardware and test developments in front of internal teams and external vendors.
Define and execute Silicon and package qualification activities (HTOL, ELFR, ESD/LU, b/HAST, THB, etc.).
Extract, manipulate, and analyze large volumes of data from Silicon and Package qualification programs (e.g. HTOL, ELFR, ESD, LU, UHAST, TCT, etc.), High Volume MFG, and field returns to identify failure mechanisms, reliability trends, and opportunities for yield and quality and reliability improvement.
Own cross-functional investigation of IC quality and reliability issues to identify root causes and develop solutions (RMA Triage, Analytics, Failure Analysis, etc.).
Develop and implement physics-based statistical Quality and Reliability models (ELF, TDDB, NBTI, HCI, Time zero failures, etc.) to predict silicon device failure mechanisms, degradation patterns, and lifetime behaviors.

Develop and implement strategies for high volume manufacturing of SoC products, including troubleshooting, ATE test coverage optimization, DPPM reduction, Test cost reduction, power and performance assurance, and product data integration and correlation between system, ATE, and System Level Test (SLT).
Drive interactions with wafer fabs and OSATs, own and drive checkpoints for key quality metrics.
Drive volume ramp and mass production through test program releases, volume data analytics, lot disposition, extended test time reduction, yield improvement, and RMA handling.
Collaborate with cross-functional teams across the globe including ATE and SLT Test Engineering, Q&R, Packaging, Supplier Management and Operations to build, deploy, and maintain a high volume manufacturing screening solution.
Support setup and maintenance of test, diagnosis, and yield analysis infrastructure, including RMA support.