דרושים » הנדסה » Quality and Reliability Engineer, Google Cloud

Collaborate with Architecture, Design and Verification teams to develop new product bring-up, validation, characterization, qualification strategies and manufacturing test solutions for new High Performance Computing (HPC) products in advanced process technologies.
Verify test solutions on pre-silicon models (simulation or emulation) and develop ATE test modules, DC tests, binning, production and characterization flows.
Develop and validate test programs on Automated Test Equipment (ATE) platforms for new product integration (NPI) in preparation for high volume manufacturing (HVM), working with ATE vendors.
Support product, volume data analysis of screening and characterization data, test time and yield improvements, assess test escapees and Return Materials/Merchandise Authorizations (RMAs), localize failures, implement containment measures and partner with design, manufacturing, quality and reliability teams to root cause and implement corrective actions.
Develop tools, flows and methodologies to improve and automate the testing.

Develop and execute comprehensive validation plans for Google's custom silicon, covering functional, performance, power, and reliability aspects.
Design and build scalable validation test infrastructure, including hardware setups, software frameworks, and automation tools on Emulation and/or FPGA platforms.
Lead the debugging and resolution of complex silicon issues, collaborating with cross-functional teams such as design, architecture, software, and firmware.
Analyze validation data to identify trends, root causes, and opportunities for improvement in silicon quality and reliability.
Build and mentor a high-performing team of silicon validation engineers, fostering a culture of collaboration, innovation, and technical excellence.

Build and mentor a high-performing team of silicon validation engineers, and foster a culture of collaboration, innovation, and technical excellence.
Develop and execute comprehensive validation plans for Google's custom silicon, covering functional, performance, power, and reliability aspects.
Design and build scalable validation test infrastructure, including hardware setups, software frameworks, and automation tools.
Lead the debug and resolution of silicon issues, collaborate with cross-functional teams such as design, architecture, software, and firmware.
Analyze validation data to identify trends, root causes, and opportunities for improvement in silicon quality and reliability.

The Chip Test Engineer plays a crucial role in designing, developing, and implementing automated test for IC chips and systems for Automotive industry. The Test Engineer is responsible to define and develop tests, design test features, program test scripts, and analyze test results to ensure the quality and functionality of products. The Test Engineer collaborates with cross-functional teams to troubleshoot issues, improve test processes, and support product development efforts.

Responsibilities:
Develop and implement test strategies, plans, and procedures for ATE systems to ensure comprehensive testing of ICs.
Design and develop test features, test programs, and test scripts for automated test environment (ATE) based on product specifications and requirements.
Collaborate with design engineers, product manager, production vendors and manufacturing teams to understand product functionality, performance requirements, and testability considerations.
Conduct feasibility studies and risk assessments to identify potential challenges and develop mitigation strategies for test development and implementation.
Develop test program based on code languages C++ , Java and Python.
Debug, troubleshoot, and resolve issues with ATE hardware, software, and test scripts to ensure reliable and accurate test results.
Analyze test data and results to identify trends, anomalies, and potential defects, and provide feedback to design and development teams for product improvement.
Develop and maintain documentation for test procedures, specifications, and configurations.
Collaborate with vendors and suppliers to evaluate and select ATE equipment, components, and software tools that meet project requirements and performance standards.
Stay abreast of industry trends, advancements in test technologies, and best practices in automated testing to drive continuous improvement in test processes and methodologies.

Develop and implement strategies for high volume manufacturing of SoC products, including troubleshooting, ATE test coverage optimization, DPPM reduction, Test cost reduction, power and performance assurance, and product data integration and correlation between system, ATE, and System Level Test (SLT).
Drive interactions with wafer fabs and OSATs, own and drive checkpoints for key quality metrics.
Drive volume ramp and mass production through test program releases, volume data analytics, lot disposition, extended test time reduction, yield improvement, and RMA handling.
Collaborate with cross-functional teams across the globe including ATE and SLT Test Engineering, Q&R, Packaging, Supplier Management and Operations to build, deploy, and maintain a high volume manufacturing screening solution.
Support setup and maintenance of test, diagnosis, and yield analysis infrastructure, including RMA support.

Lead and execute activities in the design, implementation, and verification of DFT solutions for large-scale ASICs.
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage the DFT team's workload and deliverables, provide technical leadership and guidance to the team.
Lead DFT execution of a silicon project - planning, execution, tracking, quality, and signoff.

Execute activities in the design, implementation, and verification of Design for Testing solutions for Application-Specific Integrated Circuit (ASICs).
Develop DFT strategy for hierarchical DFT, Scan, and Automatic Test Pattern Generation (ATPG).
Perform ATPG scan, cover debug and motivate design fixes for coverage and quality improvements.
Perform scan verification at Register-Transfer Level (RTL) and gate level.
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT Scan requirements are met and mutual dependencies are managed.

Participate in evaluation of future ASIC designs and general architecture for executing Googles data center networking roadmap: off-the-shelf components, vendor co-developments, custom designs, and chiplets.
Collaborate in developing new layer protocols for data center networking.
Understand how it interacts with software and other ASIC subsystems to implement groundbreaking data center networks.
Define performance hardware/software interfaces. Write micro architecture and design specifications
Define efficient micro-architecture and block partitioning/interfaces and flows

We are looking for a Senior Test Automation Engineer to join our Product Engineering Team. In this role, you will be responsible for designing and implementing automated test programs for hardware validation and production testing. You will work closely with hardware engineers to define test strategies, ensure seamless SW-HW integration, and optimize test environments to improve efficiency and reliability.

Key Responsibilities

Define and drive team SW methodologies to develop scalable and maintainable test solutions by using SW best practices
Develop and maintain automated test programs for hardware validation and production testing.
Analyze hardware schematics and component datasheets to understand DUT (Device Under Test) behavior.
Collaborate with hardware engineers to define, implement, and stabilize automated test environments.
Enable HW operation through software-driven testing methodologies.
Debug SW-HW integration issues and optimize test sequences for robustness and efficiency.
Maintain test documentation, analyze test results, and contribute to yield improvement efforts.

Develop DFT strategy and architecture (e.g., hierarchical DFT, Memory Built-In Self Test (MBIST), ATPG).
Complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high-test quality.
Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks.
Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces.
Document DFT architecture, test sequences, and boot-up sequences associated with test pins.