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In this role, as Senior Team Leader of the AI NPU Simulator, you will lead a Group developing a major part of AI simulation framework, in the core of our AI software offering. The AI NPU simulator enables the execution of state-of-the-art LLMs, Generative AI models, and neural networks with exceptional performance, impacting multiple hardware and software teams across the company.

You will drive the development of robust, scalable, and efficient simulation software, working closely with global Architecture, VLSI, and Software teams to shape next generation of AI solutions.

We are looking for an exceptional hands-on leader with strong technical expertise, proven experience leading software teams, and a track record of delivering complex, state-of-the-art products on time and with high quality. The ideal candidate is execution-driven, innovative, and passionate about building high-performing teams and cutting-edge AI technology.



Responsibilities

Manage and lead two teams (Development + Validation) .

Be accountable for the simulation lifecycle, including architecture, development, validation, and release.

Lead development of advanced simulation models for AI processors.

Own delivery of complex, multi-release roadmaps.

Ensure strong alignment between hardware design, compiler behavior, and simulation models.

Drive system-level correctness and performance accuracy.

Support system bring-up, debugging, and customer-facing activities when needed

We are looking for an exceptional hands-on leader with strong technical expertise, proven experience leading VLSI Front-End Design engineers, and a track record of delivering complex, state-of-the-art products on time and in production ready quality.

The ideal candidate is execution-driven, innovative, and passionate about building high-performing team and cutting-edge AI technology.

Responsibilities

Manage and lead a team of Front-End Design engineers.

Be accountable for the teams development lifecycle, including architecture, development, validation, and release, focusing on meeting PPAA targets.

Lead development of advanced VLSI IPs for AI processors, DSP and HW accelerators while continuing pushing the VLSI design methodologies, procedures, sign off and AI tools assimilation to its next level.

Support system bring-up, debugging, and customer-facing activities when needed

We are looking for a CAD/Emulation Graduate Engineer to join our infrastructure team. This position is designed as an entry-level role for a recent graduate, providing hands-on experience with advanced VLSI CAD/Emulation and infrastructure



Key Responsibilities

Develop and maintain automation scripts for front-end Emulation and VLSI CAD flows and automation.

Support execution and releases of VLSI artifacts while marinating advanced CAD flows.

Assist in improving infrastructure efficiency and tool integration.

Work with version control systems and CI/CD pipelines for regression and build environments.

Own and rule top notch emulation methodologies and procedures.

The System team defines and develops cutting-edge 5G technology. In this role, you will lead the system team responsible for defining our next-generation modem products and developing modem algorithms, working at the intersection of research, system design, and implementation.

Responsibilities

Lead a team of senior system and algorithm engineers responsible for developing innovative 5G modems.

Partner closely with VLSI and SW teams implementing the modem HW and SW and align on system definitions with implementation constraints.

Develop and maintain deep expertise in cellular standards and their implications for modem design.

Lead system and algorithmic research, balancing trade-offs between DSP/SW/HW implementations, performance, implementation cost, real-time constraints, and time-to-market.

Own system definitions, requirements, and implementation from initial research through simulation to official release, including MATLAB/C/C++/SystemC modeling and specification documentation.

Mentor and grow team members, fostering technical excellence and professional development.

Required Staff GPU Verification Engineer
Join our GPU Hardware Verification team in Raanana, Israel, and help shape the future of the world's most widely deployed GPU architecture - Mali. As a Staff Hardware Verification Engineer, you will play a key technical role in verifying advanced GPU components and subsystems, working alongside architects, designers and verification engineers to deliver high-quality, industry-leading graphics technology. You'll contribute to complex verification environments, solve challenging technical problems and help drive continuous improvements to our verification methodologies and flows.
Responsibilities:
Develop and execute verification plans for advanced GPU components and subsystems.
Develop and maintain AI tools, agents, and skills to support our engineering teams and workflows.
Build, maintain and enhance robust verification environments using SystemVerilog and UVM.
Apply coverage-driven, constrained-random and, where appropriate, formal verification techniques to achieve comprehensive functional coverage.
Debug complex functional issues and work closely with Design and Architecture teams to identify and resolve root causes.
Contribute to block-level and system-level verification, including environment integration and regression analysis.
Improve verification methodologies, automation, scripting and continuous integration flows to increase quality and efficiency.
Participate in verification reviews and support verification sign-off activities.
Share technical knowledge and collaborate with colleagues across the wider GPU engineering organisation.

We are seeking a Software Developer who can see the big picture. This essential role will give you an opportunity to craft and deliver a new class of user-space applications and kernel space drivers. You will join the storage software team. The team is responsible for developing storage drivers & storage emulation solutions.

What you will be doing:

End-to-end responsibility for major features in user space and kernel applications.

Maintain and enhance storage Linux Kernel drivers.

Participate in enhancing our cutting-edge technology storage solutions
Work with partners and customers worldwide.

Drive performance tuning, usability improvements, and test automation.

Our HW team designs innovative end-to-end connectivity solutions for GPU servers. Our products optimize data center performance and deliver industry-leading bandwidth and scalability. Our products are focused on delivering the most optimized power - performance communication solutions for industries like AI, ML, Cloud, Media and Entertainment as well as any other industry that can benefit from our Datastream acceleration.



What you'll be doing:

Lead Pioneering Switch System design from concept to mass production.

Collaborate and integrate with all HW project fields: Board Design, Mechanics, Thermal, PCB Layout, Production, Software/Firmware, RTL and more.

Project decision maker - Technical focal point.

The position consists of product specification definitions, electrical schematics, component selection, layout guidance, hands-on testing in a lab environment, accompanying production and qualification processes.

We are seeking a highly motivated High-Performance System Architect to join our team of experts and help shape the future of high-performance and ML / AI computing. Our next-generation NVL systems will be at the forefront of connecting and powering the world's most advanced compute clusters, from supercomputers used in AI research to high-performance clusters used at almost every industry today, such as car and Pharmaceutical. As a high-performance system architect, you will have the opportunity to work on some of the most cutting-edge technology and help to drive the innovation of our next generation networks that will be used by top researchers and engineers around the world.

What youll be doing:

Define the NVL system architecture end-to-end, by internal requirements and customers requirements through all product life cycles (post/pre silicon, on deployments).

Research of various solutions to enable the next large-scale-high-performance computing clusters. The position spans over various layers from algorithms, software, firmware, and HW.

Developing models for simulations and performance testing, analysing the results and development of future HW and SW.

Collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and research teams, to ensure the successful execution of the project.

We are looking for an outstanding Senior Networking Software Architect to join the NIC/DPU Software and Firmware Architecture group. In this role, you will help define the next generation of our datacenter and AI networking platforms, with focus on DPU management, QoS, performance, telemetry, and software architecture across stacks. You will work closely with hardware designers, firmware/kernel driver teams, system engineers, validation, product management and customers. The role spans early architecture definition, pre-silicon design, bring-up, and production readiness for large-scale AI and cloud datacenter deployments.

What Youll Be Doing:

Own software and system architecture for next-generation DPU management, QoS, performance, telemetry, and observability features.

Define end-to-end control and management flows across DOCA, host drivers, embedded firmware, BMC, management controllers and external management systems.

Specify telemetry and observability requirements, including counters, logs, traces, events, health monitoring, debug data, and streaming telemetry.

Define management interfaces and APIs for configuration, provisioning, lifecycle operations, diagnostics, and field serviceability.

Write clear architecture specifications, interface definitions, flow diagrams, and design documents for software, firmware, and system teams.

Partner with R&D teams to translate high-level architecture into implementable designs and guide features through development, validation, silicon bring-up, and production.

Analyze system performance bottlenecks, interoperability issues, telemetry gaps, and customer-reported issues, then feed learnings into future architecture.

Collaborate with system and cluster architects to ensure NIC/DPU features fit end-to-end AI datacenter and cloud networking designs.

We are seeking a Senior System Management Architect to lead the management architecture for our advanced SmartNIC cards. You will be the resident expert for SmartNIC system management, ensuring that NIC ASICs, Baseboard Management Controllers (BMCs), MCUs, CPUs, and CPLDs operate in perfect unison. You will own the lifecycle management specifications for SmartNIC platforms-from factory provisioning and day-one deployment to complex orchestrated reset flows and secure recovery. If you are someone who enjoys looking at a high-level system diagram and then immediately diving into the I2C/I3C bus topologies and PLDM command structures required to make it work, this role is for you.

What you'll be doing:

System Architecture & Flow Definition: Define and document comprehensive production, provisioning, update, recovery and reset flows for SmartNIC cards. Crucially, you will ensure that these board-level architectural decisions perfectly align with and support overarching platform-level needs, orchestrating seamless coordination between the NIC ASIC, BMC, CPU, and peripheral components.

Security & Provisioning: Specify security provisioning flows including OTP fusing, secure boot enablement, attestation key injection, certificate chain management, RPMC key derivation, and PQC (Post-Quantum Cryptography) requirements. Define IPN-to-OPN transition and component locking procedures.

Protocol Implementation & Guidance: Specify the use of standard management protocols (MCTP, PLDM, SPDM, NC-SI) across internal board interfaces to achieve secure boot, firmware updates, and telemetry gathering.

Hardware/Software Intersect: Dive deep into device-level hardware and software behaviour. Define CPLD logic requirements, power-sequencing dependencies, and reset orchestration (e.g., handling PCIe PERST#, SBR, and forced resets) for multi-host and standalone SmartNIC environments.

Interface Management: Architect intra-board communication pathways using PCIe, I2C/I3C, USB, and SPI, ensuring robust out-of-band (OOB) and in-band management connectivity.

Cross-Functional Leadership: Collaborate tightly with Production teams, Hardware and Firmware Engineering, NIC FW/Driver teams, and QA to translate your architectural specifications into implementable, testable realities.

Technical Documentation: Author rigorous technical specifications, test plans, and architectural design documents to guide both development and factory production.

Our HW team in Israel is looking for an experienced System Engineer to join the Hardware Switch Group. The team leads the development of networking infrastructure for our next-generation data centers focusing on accelerated performance while enabling optimized end to end GPU connectivity.

What you'll be doing:
CPO (Co Package Optic) Switch System architecture and design from concept to mass production.
Define the HW requirement, HW arch, board partition and lead electro-optic-mech concept. In addition - design/review HW aspects such as schematics, component selection, layout, opto-mechanics, DFM/T.
Collaborate and integrate with all HW project fields: Board Design, Mechanics, Thermal, Production, Software/Firmware, RTL and more.
The position consists of hands-on testing in lab environment for electrical and optical integration & validation, including problem solving while accompany production and qualification process.

The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The System-On-Chip (SOC) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design and verification. You should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.

In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.


What you'll be doing:

Implement chip level design through collaboration with cross-functional teams (Functional Design, DFT, Design Verification, System Verification, STA, and Physical Design).

Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, emulation, resolve design quality issues.

Daily work involves aspects of chip level design, including partitioning, CDC, RDC, trial synthesis, design quality checks.

Taking part in flows development and deployment.