We are looking for a skilled and motivated Verification engineer to join our team!
What you will do:
- Define and implement verification strategies in collaboration with cross-functional teams.
- Develop and maintain a UVM-based environment.
- Write testbenches and verification components using SystemVerilog
- Use scripting languages (e.g., Python, PERL ).
Requirements: Requirements:
- BSc or MSc in Electrical Engineering, Computer Engineering, or a related field from a well-established university.
- 5+ years of experience in ASIC design or verification.
- Strong experience with SystemVerilog and familiarity with UVM methodology.
- Effective communication skills and a collaborative mindset.
This position is open to all candidates.