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We are looking for a junior Embedded Software Engineer, to join us in building the next generation of networking products. Youll have the opportunity to work on the technologies that power the worlds largest cloud provider, in a dynamic, open, fast-paced environment. Working for Annapurna Labs is thrilling and a constant learning experience. As an embedded SW development engineer, you will be responsible for developing features for Annapurna Labs next-generation hardware, to enable high network bandwidth and packets-per-seconds (PPS) performance, with consistently low latency. You will work to bring up a broad selection of instance types, optimized for various use cases, to suit each of our customers needs, such as varying combinations of CPU, memory, storage, and networking capabilities. As a SW development engineer, you will play a key role in shaping architecture definitions and SW system designs, and help to resolve complex customer issues. You will continuously evolve technically, while working to monitor our cloud health, maintain high quality standards, develop highly-optimized code, and provide exceptional customer satisfaction.

Key job responsibilities
We will be conducting a unique onboarding training program, where you will be studying the following with our technical experts and team leaders:
* Embedded systems basics.
* Annapurna technologies in EC2.
* Cloud compute development.
* Networking 101.

As a member of the UC organization, youll support the development and management of Compute, Database, Storage, Internet of Things (IoT), Platform, and Productivity Apps services in our company, including support for customers who require specialized security solutions for their cloud services.

Take part in the development of cutting-edge products within a disruptive system architecture. You will have the opportunity to work on the technologies that power the worlds largest cloud provider, in a dynamic, open, and fast-paced environment. We provide a highly reliable, scalable, low-cost infrastructure platform in the cloud, which powers hundreds of thousands of businesses in 190 countries around the world. Annapurna Labs, as part of us, is looking for talented engineers to help us develop a semiconductor platform based on a revolutionary architecture.

Looking for exceptional senior engineers to join the top-tier team that is developing the next generation semiconductor platform, based on a revolutionary architecture. Engineers will participate in design activities, working on the next generation of our products.

You are invited to take part in developing, integrating and deploying cutting-edge technologies, starting with identification and definition of project requirements, architecture, feature development, and collaboration with the different groups.
Your design will be integrated into the nitro SoC, on millions of servers worldwide. This is an opportunity to have a large-scale impact.
As a VLSI engineer and a member of the Nitro project, you will have an impact over the device through its entire lifecycle, from the product definition stage to mass production. You will work in close collaboration with multiple groups, including Architecture, Software, Verification, Backend, and DFT.

Key job responsibilities
*Full ownership of one or more IPs within the product:
-Micro-architecture.
-RTL coding and debug.
-Synthesis and timing closure.
-Sign-off.
* Supporting the Verification and Emulation teams: Test plan, Coverage review.
* Ensuring that the chip meets quality and reliability standards.
* Collaborating with cross-functional teams, including Product Definition, Verification, Software, and Physical design.

We are looking for exceptional senior chip architects to join a world-class team that is reinventing how workloads run at scale.

As a Chip Architect, you will define architecture and micro-architecture across the complete product lifecycle - from initial requirements and early-stage technology exploration through design, implementation, and production deployment. You will explore and analyze architectural options for current and next-generation solutions, including new physical layer (PHY) and interconnect technologies, innovative protocols, and fundamental improvements to our hardware and software stack to make us the best place to run ML workloads and establish Annapurna Labs solutions as the industry-leading platform for Training and Inference workloads.

This role requires a top-down understanding of our complete solution stack, including system architecture, software stack, chip architecture, and microarchitecture. You will work in close collaboration with multiple groups - Software, Silicon engineering, System and Platform teams, and cross-functional teams across us. Your architectural decisions will influence the design of chips deployed on millions of servers worldwide, powering the future of AI, machine learning, and general-purpose compute. This is an opportunity to have large-scale impact on how the world builds and deploys infrastructure.

we are looking for a Lead SoC Architect.
Responsibilities:
Definition and detailed hardware specifications of subsystems in the SoC
Breaking down the sub-system architecture into microarchitectural blocks with the related firmware, and SW components.
Understanding the system in which the SoC is integrated to and designing the SoC to perfectly fit into the datacenter system.

Were looking for an experienced SW Team Manager to join our Simulators Team, where you'll lead the design and development of our hardware simulators - functional and performance models that serve as the source of truth, drive architectural exploration and compiler optimization.
Our simulators model diverse cores within a cutting-edge SoC designed to accelerate Big Data and Database Analytics.
You will collaborate closely with hardware and software teams, contributing to co-design efforts that influence architecture, tooling, and system-level behaviour.
Responsibilities:
Lead & grow a team of experienced engineers
Develop new hardware simulators and continue evolving existing one.
Collaborate with Architecture, VLSI, and Software teams to drive co-design initiatives.
Provide insights that influence chip architecture, compiler optimization, and system-level performance.
Develop tools that drive the chip development cycle.

we are seeking a highly technical, partner-facing Integration Engineer to join our Network team. In this role, you will be the primary technical driver for onboarding partners to the Network and maintaining quality and product excellence with existing partners.
You arent just following a manual; you are a technical consultant, a troubleshooter, and a bridge builder. You will work closely with R&D, Product, and Business, ensuring that every provider integration is seamless, secure, and scalable.
What Youll Do:
Own the Integration Lifecycle: Lead partners from initial discovery through to production go-live, serving as their dedicated technical Point of Contact.
Act as Tier 1 R&D: Deep-dive into the code to answer complex architectural questions. Youll debug, write code, analyze API logs, and solve technical hurdles.
Bridge the Gap: Translate business needs into technical requirements. Youll help partners understand how to map their existing infrastructure to our protocol.
Collaborate Cross-Functionally: Work hand-in-hand with Product to relay feedback from the field and with Business to ensure the providers commercial goals are met.
Scale the Process: Develop technical documentation, tools, and integration best practices to streamline the onboarding process and making it more intuitive.

Nuvoton Israel is a leading supplier of SoCs, microcontrollers and security hardware solutions for tier-1 customers in the computing and server business. A self-contained design center, spanning from product management, system and chip architecture, through design, software development, system engineering and production. Our products combine unique sets control, management, and advanced security solutions, enabling our customers to establish differentiation in their end markets. We are looking for a Chip Design Verification engineer to join our Verification team! This is your opportunity to have an impact on the design of millions of computers sold worldwide each year by leading brands.
The role includes: - Building complex verification environments - Meeting the challenges presented by state-of-the-art design - Continues professional growth using the most advanced tools and methodologies - Use AI for improved productivity

As a Senior AI Engineer on the Guardian Agents team, you will develop both our autonomous "digital employees" that execute security programs and the Control Plane that governs them. You will build a platform that allows customers to calibrate agents through conversation, ensuring human feedback is transformed into persistent organizational knowledge. By engineering these closed-loop systems, you enable agents to learn, evolve, and deliver accurate, goal-driven security outcomes at scale.
What Youll Do:
Architect Autonomous Agents: Build goal-driven agents for complex security tasks like false-positive reduction and automated triage.
Build the Control Plane: Develop the infrastructure for Human-in-the-Loop (HITL) feedback, natural language calibration, and stateful memory systems.
Engineer for Growth: Implement evaluation frameworks and "organizational memory" to ensure agents stay accurate and follow historical security precedents.
Bridge AI & Engineering: Collaborate in a "Core Pod" with Security Researchers and Data Scientists to turn raw security signals into scalable, productized agent behaviors.
Scale Data Pipelines: Integrate agents with Big Data foundation to ensure real-time context and tenant-safe execution.

We are looking for a RT SW Developer.

we are seeking for a Verification engineer. We are seeking a highly skilled Verification engineer to join a Processor Verification team working on nextgeneration processor cores. In this role, you will take a key part in verifying critical processor blocks, collaborating closely with architecture and design teams to ensure functional correctness. You will own verification activities endtoend from TEST planning and environment development to execution, coverage analysis, and closure- using advanced verification methodologies.

The role includes development of Automated TEST Equipment (ATE) TEST stations, including digital tests and RF tests. The engineer will be responsible for TEST system development from the requirements definition stage through delivery of the TEST system to the customer and its maintenance. The role also includes technical characterization and definition of project documents such as SPEC, SOW, TRD. Education Required: Bachelors degree in Electrical Engineering.

In this role, you can lead our teams to deliver fully functional "first silicon" IP designs, from defining initial constraints through high-quality tape-out. You will have the rare and rewarding privilege of crafting upcoming products that will delight and inspire millions of customers every single day.
Responsibilities
Own the entire IP-level netlist generation and timing convergence journey, from synthesis and UPF power intent to final sign-off.
Architect and manage complex timing constraints (SDC) for both standard and custom designs, ensuring sign-off quality from day one.
Drive Full Chip and block-level timing/noise convergence, including hierarchical timing flows and power optimizations.
Collaborate closely with RTL designers to understand clock architecture, DFT teams on mode constraints, and PNR teams to achieve flawless physical convergence.
Develop and support automated block and chip-level sign-off flows, working with CAD teams to shape cutting-edge methodologies that eliminate pessimism and accelerate convergence.
Perform deep-dive signal integrity (SI) and noise analysis, drive custom IP integration, and generate block-level budgets to ensure correlation with the Full Chip.

This is a highly visible role where you will own the physical design cycle at the partition, IP, and Chip levels-enabling us to produce fully functional "first silicon" designs. Do you love working on challenges that no one has solved yet? If you are ready to join the world's leading engineers and work with state-of-the-art design flows, come join our group.
Responsibilities
You will be responsible for all phases of pre-silicon development, from initial definition to high-quality tape-out (Netlist to GDSII).
Lead block-level Place & Route (PnR), complex floor-planning, partitioning, and the creation of power domains and grid specifications.
Develop and validate high-performance, low-power clock network guidelines and distribution.
Drive static timing closure (STA), Physical Verification (DRC/LVS), and Electrical/Power analysis (EM, IR-Drop, Xtalk, and Noise).
Participate in establishing CAD and physical design methodologies for "correct-by-construction" designs and assist in flow development for chip integration.
Generate and implement ECOs to fix timing, noise, and EM/IR violations while meeting strict area and power constraints.
Work closely with logic design teams on SoC architecture and HDL (Verilog) to implement timing fixes and design optimizations.

Appdome’s mission is to protect every mobile app in the world and the people who use mobile apps in their lives and at work.
Appdome provides mobile brands with the only patented, centralized, data-driven Mobile Cyber Defense Automation platform, delivering rapid no-code, no-SDK mobile app security, anti-fraud, anti-malware, anti-cheat, anti-bot implementations, configuration as code ease, Threat-Events™ threat-aware UI/UX control, ThreatScope™ Mobile XDR, and Certified Secure™ DevSecOps Certification in one integrated system.
With Appdome, mobile developers, cyber and fraud teams can accelerate delivery, guarantee compliance, and leverage automation to build, test, release, and monitor the full range of cyber, anti-fraud, and other defenses needed in mobile apps from inside mobile DevOps and CI/CD pipeline.
Leading financial, healthcare, m-commerce, consumer, and B2B brands use Appdome to upgrade mobile DevSecOps and protect Android & iOS apps, mobile customers, and mobile businesses globally. Today, Appdome's customers use their platform to secure over 50,000+ mobile apps with protection of over 1B mobile end users projected. About The Position We are looking for a talented Mobile Fraud Engine to join Appdome. In this role, you will develop sophisticated fraud detection and prevention components that operate at the core of our mobile threat intelligence platform — diving into signal processing, risk evaluation logic, and real-time decision-making, and translating your findings into robust, production-ready code. This position is ideal for developers who want to understand how fraud happens and use that knowledge to build innovative solutions that protect millions of mobile applications worldwide. Job Description
* Design, develop, and maintain core fraud detection and risk-scoring components within mobile apps.
* Investigate fraud patterns and mobile threat signals to develop innovative detection and prevention mechanisms.
* Own the collection of threat and device signals used by risk assessment algorithms to perform device and user behavioral profiling.
* Design systems that make split-second decisions, balancing security accuracy with user experience.
* Continuously explore emerging fraud trends and incorporate new detection techniques into our product.
* Collaborate with a multidisciplinary team of engineers, data scientists, and security experts to deliver end-to-end solutions.