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A Sisram Medical company, is a global leader in medical-aesthetic technologies, with over 25 years of experience in energy-based devices (EBD). Over the years, we have evolved into an integrated aesthetic and wellness ecosystem that combines medical devices, injectables, diagnostics, and personalized skincare. The company operates in a dynamic, innovation-driven environment, merging advanced technology with deep clinical understanding to create holistic solutions for aesthetic clinics. Our headquarters are in Caesarea, Israel, with business operations in more than 100 countries worldwide.
How your day will be?
* B.Sc. student (2nd-3rd year) in Computer Science, Software Engineering, or a related field.
* Good programming skills and ability to understand existing codebases.
* Knowledge of object-oriented programming principles.
* Experience with Git and version control.
* Basic understanding of SQL and relational databases.
* Understanding of REST APIs and JSON.
* Familiarity with client-server and cloud architectures.
* Good analytical and troubleshooting skills.
* Ability to work independently and learn quickly.
* Fluent English (spoken and written).

We are seeking a senior embedded software engineer to serve as the technical lead for our embedded team, developing the real-time software at the heart of a first-in-market surgical robotic platform.

This is a hands-on, individual-contributor role: you will help shape the technical direction, make sound engineering decisions, and take ownership of delivering features end to end, while remaining deeply involved in the code. As the system is designed collaboratively by the team, strong cross-team collaboration is as important as individual technical excellence. This is safety-critical software, and we hold a high standard for rigorous design, testing, and code quality.

Responsibilities:

Serve as the technical and feature lead for the embedded team, guiding design decisions and mentoring peers through code reviews (this is not a people-management role).
Drive the design and development of our real-time embedded software, and own the delivery of features end to end.
Uphold a high standard of code quality through code reviews, best practices, and continuous improvement.
Remain hands-on, personally developing the most complex and safety-critical components in C/C++.
Collaborate closely with other teams across the company to ensure technical alignment and shared progress.
Take ownership of delivery, ensuring features are completed on schedule and to the quality this product demands.
Make technical decisions independently where appropriate, while knowing when to involve the wider team.

The Senior Software Engineer, Edge our company's growing engineering organization and help build the software that runs on the core device layer behind our platform. This role sits within a small, highly impactful team responsible for a hybrid edge system that powers core functionality across video, security, networking, storage, and AI deployment in production environments. You'll work on a resource-conscious, distributed device architecture that spans multiple hardware targets and brings together technologies more commonly seen across both embedded and cloud systems. This is a strong fit for an engineer who enjoys meaningful ownership, thrives in a fast-moving startup environment, and is comfortable building reliable software for systems customers depend on every day.
Location & Travel
Hybrid / Onsite Schedule: Based in Caesarea or Ramat Gan with 2 days a week working from home.
Responsibilities
Contributing to the development of our core edge platform, designed to run across diverse hardware environments as part of a hybrid edge-cloud architecture
Developing and integrating video management capabilities, including streaming, recording, and real-time AI processing
Designing and optimizing systems for low-latency, high-performance workloads at the edge
Building secure and efficient communication pipelines between edge devices and cloud systems
Working closely with AI/ML engineers to deploy and optimize models on-device
Participating in code reviews, debugging, and performance tuning across the stack
Collaborating with a talented team of engineers, AI experts, and leadership in a fast-moving environment
We dont do cookie-cutter. If you dont check every box but youve got the grit, the drive, and the track record-especially in security or AI-we encourage you to apply.

we are seeking a Lead System Architect to join our system architecture team and help define NR-NEXUS, our next-generation AI inference platform.

Responsibilities

Lead the software architecture and technical roadmap for NR-Nexus
Write system specifications for NR-Nexus product
Research AI infrastructure, SaaS platforms, model serving, and inference trends
Work with engineering to translate technical capabilities into product value
Work closely with engineering teams to optimize performance, scalability, and feature delivery.
Define performance goals and lead profiling, benchmarking, and optimization efforts for GenAI and distributed AI workloads.
Collaborate with customers, partners, and open-source communities to ensure ecosystem compatibility and adoption.
Mentor software engineers and provide technical leadership

A significant part of the role involves building end-to-end integration flows and tests, particularly around token generation pipelines and system orchestration, as well as contributing to intelligent system behavior such as hardware selection and execution strategies. The role also includes developing system-level logic in Python for multi-tenant management, caching strategies, and service lifecycle management across the platform.

***This is not a Data Science position***

Responsibilities:

Build and maintain end-to-end integration flows across the AI inference pipeline (serving, orchestration, APIs, and infrastructure)
Design, implement, and optimize LLM inference workflows, including prefill and decode stages
Improve system performance with focus on throughput, latency, and interactivity
Write production-grade components in Python and integrate them into the broader system
Contribute to system-level logic such as smart hardware selection and execution strategies
Integrate models (open source and custom), services, and APIs into cohesive, reliable end-to-end application pipelines

We are looking for a Senior Software Engineer to help build and optimize large-scale, high-performance GenAI infrastructure and inference systems on Kubernetes.

As AI workloads increasingly move toward Kubernetes-native infrastructure, we are building systems that support distributed inference, performance optimization, reliability, observability, and production-grade deployment at scale.

This role is ideal for an engineer who can reason deeply about systems, performance, tradeoffs, and reliability, and who is comfortable owning difficult technical decisions end-to-end.

You will work across inference serving, distributed systems, optimization, and Kubernetes-native AI infrastructure.

What Youll Do

Build and optimize high-performance Kubernetes-native GenAI inference systems
Work with modern inference stacks such as vLLM, SGLang, TensorRT-LLM, and related tooling
Work with Kubernetes-native distributed LLM inference frameworks such as llm-d and NVIDIA Dynamo
Design and implement optimization algorithms and performance improvements
Improve reliability, observability, deployment, and operational maturity of AI systems
Make architectural decisions and take ownership of technical outcomes
Collaborate with a small, senior engineering team focused on performance and production quality

AI scale-out communication is a critical element in modern data centers, and emerging standards such as Ultra Ethernet aim to address this challenge. This role focuses on defining a high-performance Smart NIC architecture optimized for GPU-centric AI workloads, with emphasis on low-latency, high-bandwidth data movement.

You will work across hardware and software domains, collaborating closely with AI, platform, driver, and VLSI teams to design a competitive scale-out networking solution.

Responsibilities

Lead the software architecture and technical roadmap for or next-generation ultra low-latency AI-SuperNIC software stack, including drivers, firmware, libfabric, and libibverbs.
Define the partitioning and interfaces between hardware, firmware, kernel drivers, user-space libraries, and AI frameworks.
Lead the design and implementation of high-performance networking, RDMA, and GPU-direct communication capabilities.
Drive software support for emerging technologies and standards such as UEC, UALink, MRC and RoCEv2 ecosystems.
Work closely with hardware, system architecture, and VLSI teams to optimize performance, scalability, and feature delivery.
Define performance goals and lead profiling, benchmarking, and optimization efforts for GenAI and distributed AI workloads.
Collaborate with customers, partners, and open-source communities to ensure ecosystem compatibility and adoption.
Mentor software engineers and provide technical leadership across firmware, driver, and networking software development

Join our architecture team, the core of silicon development .
Our architects manage all aspects of system chip development and provide specifications to various development teams. In this role you will:
Define the features and specifications of future devices.
Utilize a data-driven approach to model and analyze networks of tomorrow, providing optimal solutions for our customers.
Model, analyze, and present simulation results for cutting-edge networking solutions across various use cases.
Apply strong networking research skills and a robust theoretical background to your work.

Come join us and help shape groundbreaking solutions by designing, developing, and testing some of the most complex ASICs in the industry.
What You Will Do:
In this role, you will be part of the Switch ASIC Post-Silicon Electrical Validation (EPSV) team.
Ensure the ASIC operates according to specifications and reliably over time by performing extensive, high-precision measurements using advanced test equipment and procedures.
Conduct deep-dive investigations, integrating knowledge across hardware, software, and system domains to identify root causes of observed device behavior.
Handle all chip validation aspects, including:
Building validation plans.
Performing EPSV using advanced test and measurement equipment.
Writing tests in Python over device SDK.
Executing tests and analyzing results.
You will gain in-depth knowledge of chip architecture, functionality, and operating modes, enabling you to debug and resolve electrical chip-related issues.

We are excited to announce that the Cisco Silicon One team is undergoing rapid growth, and we are looking for a C++ Software Developer.
Meet the Team:
Join the Cisco Silicon One team developing a unified silicon architecture for web-scale and service provider networks. Cisco's silicon team provides an outstanding, unique experience for ASIC and Software engineers by combining the resources offered by a sizable multi-geography silicon organization with the startup culture and breadth of growth opportunities that working in a smaller team can provide.
Your Impact:
Craft and develop software driving the world's most complex infrastructures
Gain intimate knowledge of world-class silicon and programming models
Work with architecture and design teams to define the next generation of ASIC products being developed

we are seeking a highly motivated and experienced Senior Software Engineer for a position focused on developing innovative network device monitoring and visualization solution.
Meet the Team:
This position is part of organization, based in Israel. Silicon One is the foundation of industry-leading networking hardware products, pushing the boundaries of technology and driving the next generation of high-performance, scalable solutions.
Your Impact:
Design and develop visualization capabilities within our SDK environment
Lead the development of a brand-new comprehensive self-monitoring system for network devices from the ground up
Implement a comprehensive model for capturing and managing network state information
Drive cross-team collaboration and technical strategy
Work closely with senior technical leadership
Create and refine technical requirements and system designs
Build new systems and frameworks from the ground up

We are looking for an experienced Design Verification engineer to join our DFT team and help establish and grow DFT DV activity in the Cisco SiliconOne DFT team. This role is relevant for engineers with experience in DV roles, either in DFT DV or in other verification domains, who are interested in becoming familiar with DFT design, verification methodologies, and the challenges of validating testability features in advanced silicon.
Your Impact:
Lead and drive DFT verification activities within the Cisco SiliconOne DFT team.
Develop verification plans, environments, checkers, assertions, and coverage models for DFT features.
Verify DFT architecture and implementation in close collaboration with DFT, design, architecture, and verification teams.
Work on verification of scan, MBIST, IJTAG/JTAG, test access mechanisms, DFT controllers, and related SoC-level test features.
Debug complex pre-silicon issues across RTL, verification environments, and DFT logic.
Contribute to scalable methodologies, reusable verification components, and best practices for DFT DV.
Help bridge between general DV methodologies and DFT-specific design and verification needs.

Come join us and help shape groundbreaking solutions by designing, developing, and testing some of the most complex ASICs in the industry.
In this role, you will be part of the Switch ASIC Post-Silicon Electrical Validation (EPSV) team.
Ensure the ASIC operates according to specifications and reliably over time by performing extensive, high-precision measurements using advanced test equipment and procedures.
Conduct deep-dive investigations, integrating knowledge across hardware, software, and system domains to identify root causes of observed device behavior.
Handle all chip validation aspects, including:
Building validation plans.
Performing EPSV using advanced test and measurement equipment.
Writing tests in Python over device SDK.
Executing tests and analyzing results.
You will gain in-depth knowledge of chip architecture, functionality, and operating modes, enabling you to debug and resolve electrical chip-related issues.

Join our architecture team, the core of silicon development .
Our architects manage all aspects of system chip development and provide specifications to various development teams. In this role you will:
Define the features and specifications of future devices.
Utilize a data-driven approach to model and analyze networks of tomorrow, providing optimal solutions for our customers.
Model, analyze, and present simulation results for cutting-edge networking solutions across various use cases.
Apply strong networking research skills and a robust theoretical background to your work.