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Required Silicon Engineering Manager
Modiin, Israel Full-time
Responsibilities
Perform silicon process and chip-level data analysis, establishing correlation between chip and wafer performance.
Lead process debug and yield loss analysis at chip/wafer level, driving root cause investigations and corrective actions.
Manage engineering approval forum to release production material.
Collaborate closely with vendors to implement new product tests and resolve technical/process issues.
Act as a key interface between design, testing, and production teams, ensuring alignment across the product lifecycle
Oversee and coordinate the transfer of data related to silicon design, testing, fabrication, and characterization between Production and R&D departments.
Develop and implement data management strategies to ensure data accuracy, security and accessibility.
Maintain proper documentation of data transfer protocols, version control, and data integrity checks.
Support data analysis efforts to improve silicon performance, yield, and quality.
Ensure compliance with company policies and industry standards related to data security and confidentiality.

We are looking for a hands-on Process Engineer to lead manufacturing process development, optimization, and reliability improvement for advanced LiDAR systems.
This role focuses on scaling high-precision opto-mechanical assemblies from RnD to NPI to Mass production while ensuring quality, stability, and automotive compliance.
You will work closely with R&D, Mechanics, Quality, Supply Chain, and Production teams to drive process robustness and yield improvement.
What Youll Do :
Develop, validate, and optimize manufacturing processes for opto-mechanical assemblies
Lead NPI transition from development to production (DFM / DFT support)
Define and implement PFMEA, Control Plans, SOPs, and Work Instructions
Perform process capability analysis (Cp/Cpk), SPC, and GR&R studies
Conduct root cause investigations (8D, 5 Why, Fishbone)
Drive yield improvement and scrap reduction initiatives
Lead DOE activities for process window optimization
Support automation integration and equipment qualification
Improve cycle time and line balancing
Work with CMs and suppliers to ensure process stability and automotive compliance

join our advanced packaging team to define and develop cutting-edge semiconductor package solutions for automotive-grade digital and RF system -on-chip ( SOC ) products.
youll collaborate with internal teams and external osats to deliver high-performance, manufacturable, and reliable packages that meet stringent automotive standards.
what will your job look like:
define and specify advanced package architectures for digital socs and RF ics in automotive applications.
perform substrate design for flip-chip bga (fc-bga) packages, including stack-up, routing, and ball-out optimizations.
evaluate and select substrate technologies, materials, and package solutions based on performance, cost, and reliability.
collaborate with osats to define and validate assembly materials and process flows.
work closely with internal teams such as backend, sipi, product engineering, and quality & reliability to ensure seamless integration.
monitor yield, quality, and manufacturability across package development and production stages.
support dfm reviews and ensure compliance with automotive standards and customer requirements.

in this role, you will help build socs by driving quality and reliability processes from the integrated circuit (ic) perspective. working with various cross-functional teams, you will develop quality and reliability specifications, develop and deploy design guidelines, and develop and execute TEST plans. within the larger organization, you will collaborate with global hardware quality and reliability, silicon design, validation, and engineering teams. you will have an understanding of ic flows, wafer processing, testing, qualification, yield, reliability, and failure analysis.the ml, systems, & cloud ai (msca) organization at google designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all google services (search, youtube, etc.) and google cloud. our end users are googlers, cloud customers and the billions of people who use google services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including google clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
define and lead qualification hardware and TEST developments in front of internal teams and external vendors.
define and execute silicon and package qualification activities (e.g., htol, elfr, esd/lu, b/hast, thb, etc.).
extract, manipulate, and analyze large volumes of data from silicon and package qualification programs (e.g., htol, elfr, esd, lu, uhast, tct, etc.), high volume mfg, and field returns to identify failure mechanisms, reliability trends, and opportunities for yield, quality, and reliability improvement.
own cross-functional investigation of ic quality and reliability issues to identify root causes and develop solutions (e.g., rma triage, analytics, failure analysis, etc.).
develop and implement physics-based statistical quality and reliability models (e.g., elf, tddb, nbti, hci, time zero failures, etc.) to predict silicon device failure mechanisms, degradation patterns, and lifetime behaviors.