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As a Digital Backend Design Engineer, you will be responsible for the physical implementation of digital designs from RTL to GDSII, leveraging cutting-edge EDA tools and methodologies. You will collaborate closely with RTL design, DFT, and packaging teams to achieve optimal performance, power, and area (PPA), while meeting stringent timing and yield targets.

Required Skills and Experience
Masters or PhD degree in Electrical/Electronic Engineering or a related field.

4+ years experience in digital IC backend implementation.

Proficiency with backend EDA tools, particularly Cadence Innovus and Genus.

Strong understanding of place & route (P&R), static timing analysis (STA), DRC/LVS verification, IR drop, and electromigration (EM) analysis.

Experience with advanced technology nodes (22nm or below preferred).

Skilled in Tcl scripting for automation of backend flows.

Experience in hierarchical or full-chip implementation is preferred.

Language: English at a proficient level. French is a plus.

We are seeking a Senior Guidance Engineer to play a critical role in the development of next-generation drone platforms.

This position focuses heavily on guidance and mission-level decision-making for high-performance aerial systems operating in dynamic, real-world environments.

You will design and deploy guidance and motion planning algorithms that enable precise, high-speed maneuvers and complex mission execution. This role blends analytical rigor with creativity, tackling problems that often have no textbook solutions. Youll collaborate closely with hardware, embedded software, and perception teams to bring advanced autonomy from concept to flight.

Key Responsibilities

Design, develop, and optimize guidance and motion planning algorithms for autonomous drones
Define mission-level behaviors and guidance logic, balancing performance, safety, and robustness
Implement real-time control interfaces to execute trajectories reliably in uncertain conditions
Work closely with embedded software, mechatronics, and perception teams to ensure seamless integration
Identify and address edge cases and failure modes, building resilience and graceful degradation
Stay current with advancements in drone autonomy, guidance, motion planning, and control

An Israels leading provider of SaaS-based software solutions for comprehensive Human Capital Management, is seeking for an experienced System Analyst to join an innovative team focused on developing and implementing AI-based solutions. This role involves leading end-to-end system analysis processes for complex systems, working closely with development, data, and business teams.



Responsibilities:

Analyze business needs and translate them into functional and technical specifications
Define and design AI-based systems
Collaborate with stakeholders including business users and development teams
Support development, testing, and implementation processes
Define and document system integrations and APIs

We are at the forefront of the AI revolution, delivering brand new accelerated compute platforms for global impact. Our Network Architecture group is seeking a talented and motivated Sr. Software Engineer to build the agentic workflows that our architects use in their daily work. The software at the center of this role is our hardware network simulation environment - you will design multi-step agent workflows over it, engineer the context that grounds them in our own specifications and source code, and optimize their runtime performance. If you are passionate about building the practical infrastructure that brings intelligent agents to life, we want to hear from you.


What you'll be doing:
Build agentic workflows - loops, graphs, and multi-step pipelines - that carry real hardware network simulation and analysis work end to end.
Engineer the context these workflows run on, turning our simulation models, specifications, design documents, and source code into context that makes agents accurate in our domain.
Work closely with network architects to understand their workflows and translate them into agent workflows they use daily.
Optimize the runtime performance of our simulation tooling on these platforms, including execution time, compute cost, and end-to-end latency.
Define evaluation and regression testing for agent workflows, so that changes to a prompt, a graph, or a context source are measurable.
Build observability across agent runs: what the agent did, where it failed, and why.
Champion guidelines for secure and reliable agent workflows, including data handling, access control, and interaction boundaries.
Serve as a key technical resource for solving sophisticated integration issues between agents and internal tooling.

We are seeking an AI Networking Architect to join the Networking Research Group. This role bridges the gap between emerging AI workloads and the data center infrastructure that powers them, working at the intersection of AI applications, distributed systems, networking hardware, and software architecture. You will join a focused team of multidisciplinary engineers driving AI workload optimization through deep application understanding, network analysis, and end-to-end systems thinking. Your insights will directly shape our products across the full stack - from applications and software libraries to hardware architecture and physical design.


What you'll be doing:
Model the performance of complex AI workloads to identify bottlenecks and recommend system-level optimizations.
Analyze new AI models, distributed training techniques, and inference workloads to understand their infrastructure requirements.
Build simulation and hardware platforms, run real AI workloads on them, and develop analytical tools to evaluate trade-offs across compute, memory, storage, and network behavior.
Translate research insights and workload behavior into actionable software, xhardware, and networking architecture requirements.
Partner with architecture, software, and product teams to influence our future networking and AI infrastructure roadmaps.
Drive architectural innovation by applying deep workload analysis to production machine learning frameworks.

We are looking for best-in-class Chip Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in designing our groundbreaking and innovative chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What you will be doing:

Join the Tel Aviv or Beer-Sheva group, working on RiscV processors platform.

Verification for chip blocks according to specifications under challenging constraints and with high orientation to power, area and performance.

Daily work might involve any or all aspects of chip development including verification, integration, debug

Work closely with firmware and other groups around the globe.

We are seeking a passionate QA Engineer to join our FW testing team. This position will be part of our growing team, helping NVIDIA products meet industry-leading benchmarks for efficiency and quality. As a Firmware QA Engineer, you will be immersed in the latest advancements and actively contribute to developing world-class products. Your efforts will directly impact the performance and quality of our offerings, ensuring they consistently meet industry-leading standards.


We are looking for ideal candidates who will actively test industry-leading features in the FW sector, quickly learn new features, conduct both manual and automated testing, and contribute to the development of automation systems.


What you'll be doing:
Review arch design and requirements documents for new features introduced in the Nvlink program.
Join the effort of QA shift left towards simulation for NVL7 generation.
Design, develop, and perform tests for the new features, as part of FW GA or update releases.
Automate newly added tests in the existing automation framework, and add new capabilities and features to the framework.
Report bugs found during execution, assist with reproduction and debugs to understand root cause, verify bug fixes provided by R&D team, and raise if not fixed.
Fully collaborate with different external teams like : :product marketing, R&D, and verification.
Define and build setups topologies for appropriate product coverage.

We are looking for a Senior Software Engineer to join the DOCA SDK Verification team. The DOCA SDK enables developers to rapidly create applications and services on top of our BlueField data processing units (DPUs), leveraging industry-standard APIs. With DOCA, developers can deliver breakthrough networking, security, and storage performance by harnessing the power of our DPUs.

What you will be doing:
As a Senior Software Engineer in the DOCA verification team, you will play a key role in designing and developing the verification infrastructure for the DOCA SDK. This infrastructure is a complex system that executes thousands of tests every night across multiple hardware platforms and configurations. It includes mechanisms for error handling and fault recovery, while test results are stored, analyzed using advanced tools, and presented through live dashboards and reports. Your expertise in building robust and efficient verification systems will be critical to ensuring the reliability and quality of our software.

We are looking for an experienced DFT Design Engineer to join the DFT design team and develop the next generation DFT technologies.

As a design engineer in the DFT design team, you will participate in definition and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and sophisticated products, our DFT solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.



What you'll be doing:

In this position, you will be responsible for defining, coding and integrating sophisticated DFT components into various projects and using state-of-the-art technologies.

As a member of our DFT design team, you will participate in defining various DFT features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.

Strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.

We are seeking a highly skilled and versatile Performance Research and Analysis Manager to join our Performance Group. This role will drive end-to-end performance strategy and execution for our next-generation data centers and solutions based on GPU systems, NIC, Switch, DPU and Networking technologies. The ideal candidate will oversee, evaluating, and optimizing end-to-end AI GPU cluster-level performance for scaling out large scale distributed training and inference jobs communication. The role will focus heavily on RDMA, Networking Protocols, Collective Communication, Congestion Control, and Load Balancing algorithms. Secondarily, you will lead our DPUs and Storage technologies for N-S use cases to support AI Inference jobs. Third, you will drive our Performance Dashboards and Observability for cluster-level performance analysis from a stream line telemetry across NICs, Switches, GPUs, and NVlink.

What you'll be doing:

Drive end-to-end performance strategy, characterization, test plans, and optimization for our next-generation AI GPU clusters, focusing on large-scale distributed training and inference workloads.

Deeply evaluate and optimize our Networking core technologies performance, including RDMA/PRDMA, networking protocols, collective communication (NCCL), congestion control, and load-balancing algorithms.

Work on performance research and analysis of our DPUs and storage technologies in North-South (N-S) use cases and deployment scenarios to maximize performance and efficiency for AI inference jobs.

Drive the strategy for performance observability and dashboards across our next-generation data center solutions and supercomputers by leveraging scalable, streamlined telemetry pipelines to build performance dashboards and automated analytics based on real-time performance metrics across NICs, Switches, GPUs, and NVLink boundaries.

Perform deep root-cause analysis (RCA) on complex multi-node performance bottlenecks, driving actionable mitigation plans across hardware, firmware, and software teams.

We are looking for a Chip Design Manager to join our Switch Silicon team. As a Chip Design Manager in our Networking Business Unit, you'll join a group of passionate professionals to design and lead the implementation of the next generation of state-of-the-art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!


What You'll Be Doing:

Lead a team of design and verification engineers that develops core units within the Switch Silicon.

Handle micro-architecture for RTL and simulation environment planning for units and modules.

Be responsible for the delivery of complex RTL units and their verification.

Work closely with multiple teams within the organization, such as Architecture, Full Chip, Micro-Architecture, BE, and FW.

We are looking for an experienced Design Verification engineer to join our DFT team and help establish and grow DFT DV activity in the Cisco SiliconOne DFT team. This role is relevant for engineers with experience in DV roles, either in DFT DV or in other verification domains, who are interested in becoming familiar with DFT design, verification methodologies, and the challenges of validating testability features in advanced silicon.

Your Impact
Lead and drive DFT verification activities within the Cisco SiliconOne DFT team.

Develop verification plans, environments, checkers, assertions, and coverage models for DFT features.

Verify DFT architecture and implementation in close collaboration with DFT, design, architecture, and verification teams.

Work on verification of scan, MBIST, IJTAG/JTAG, test access mechanisms, DFT controllers, and related SoC-level test features.

Debug complex pre-silicon issues across RTL, verification environments, and DFT logic.

Contribute to scalable methodologies, reusable verification components, and best practices for DFT DV.

Help bridge between general DV methodologies and DFT-specific design and verification needs.

We are seeking a talented and driven Senior Software Verification Engineer to join our innovative team and tackle SW verification challenges in the domains of high-speed networking, virtualization, and security. You will play a key role in validating and testing complex software products that support Ethernet and InfiniBand protocols, delivering advanced networking, storage, and security services for cloud, compute, and AI workloads.

What Youll Be Doing:

Develop and Automate Testing: Design, implement, and maintain automated test scripts and frameworks (primarily in Python) to verify the correct functionality of our software products.

End-to-End Feature Ownership: Deep dive into feature sets, taking responsibility from test planning through to final implementation and full automation.

System & Integration Validation: Validate software functionality and performance through system-level and integration testing, utilizing Linux-based environments and virtualization tools.

Test Environment Management: Set up, maintain, and optimize test environments using Linux, Docker, virtual machines, and other modern tools.

Collaboration & Communication: Work closely with software, DevOps, architecture, and product teams to define test requirements, coordinate releases, and ensure high-quality product delivery.

Continuous Improvement: Drive design verification flows, contribute to methodology improvements, and leverage planning/tracking systems to manage release progress and build release indicators.

Defect Analysis: Analyze test results, file defects, and track issues to closure, ensuring robust and scalable solutions.

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:
Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part inflows development.

We are looking for best-in-class STA (Static Timing analysis) Physical Design Engineers to join our outstanding Networking DFT team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you will be doing:
DFT STA execution, from rtl driven constraints and definitions through DFT constraints quality assurance to STA sign-off.
Be part of a unique team of experts who have deep understanding in all aspects of pre and post silicon.
Be exposed and work on a variety of challenging designs, unique DFT solutions that require deep silicon implementation understanding.
Daily work involves all aspects of static timing analysis - constraints, environment, models generation and timing ECO generation for block level and full chip level.
Taking part in flows development.