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we bring connectivity and intelligence to everyday products and packaging; things previously disconnected from the internet of things. our platform combines cloud services and iot pixels, computing elements that can power themselves by harvesting radiofrequency energy. this revolutionary mixture of cloud and semiconductor technology is used by some of the worlds largest brands, food, and pharmaceutical companies to change how we make, distribute, sell, use, and recycle products. our investors include amazon, verizon, ntt docomo, qualcomm, pepsico, and softbank vision fund 2. join us and help pave the way for the new iot.
our TEST & product team is responsible for keeping a target of a very aggressive cost limit of the production testing (wafer sort) while performing comprehensive testing of all the units functionalities. this involves:
development of the tests using the teradyne uf tester.
development of unique and advanced TEST hw.
monitoring and analyses the production data.
fa (failure analysis) when issues are discovered.
innovative dft (design for testability) with the design team.
responsibilities:
development of wafer sort TEST programs through a close relationship with the system team.
development of the future products dft and dfm through close collaboration with the design team.
improvement of the production data analysis and reports through close relationships with the cloud and data teams.
working with the external abroad TEST houses.
decision-making based on massive data analysis (pass criteria, improvements of the tests, identification of failures).
integrate new and innovative testing methods for a new technology sector.
specify and work with external vendors for the tester hw (probe-card and load-board).
specify and work with external vendors for the htol hw, TEST program.

the company was founded by the team that invented one of the technologies at the heart of 5g. their next vision was to develop an iot sticker, a computing element that can power itself by harvesting radio frequency energy, bringing connectivity and intelligence to everyday products and packaging, things previously disconnect from the iot. this revolutionary mixture of cloud and semiconductor technology is being used by some of the worlds largest consumer, retail, food and pharmaceutical companies to change the way we make, distribute, sell, use and recycle products.
our investors include softbank, amazon, alibaba, verizon, ntt docomo, qualcomm and pepsico.
we are looking for a talented and experienced engineer to take part in the verification efforts for the companys core product. this position involves building and maintaining a complex verification environment, and defining and executing a TEST plan. in this role, you will be leading all aspects of verification and will have a critical impact on the company's r&d path.

the company was founded by the team that invented one of the technologies at the heart of 5g. their next vision was to develop an iot sticker, a computing element that can power itself by harvesting radio frequency energy, bringing connectivity and intelligence to everyday products and packaging, things previously disconnect from the iot. this revolutionary mixture of cloud and semiconductor technology is being used by some of the worlds largest consumer, retail, food and pharmaceutical companies to change the way we make, distribute, sell, use and recycle products.
our investors include softbank, amazon, alibaba, verizon, ntt docomo, qualcomm and pepsico.
we are looking for a talented and experienced engineer to take part in the verification efforts for the companys core product. this position involves building and maintaining a complex verification environment, and defining and executing a TEST plan. in this role, you will be leading all aspects of verification and will have a critical impact on the company's r&d path.
responsibilities:
define and implement robust sv/uvm verification solutions, including TEST benches and methodologies, to drive efficient verification closure across block-level and full-chip designs, integrating mix-signals SOC simulation environment using verilog, matlab, hw/sw co-simulation and lab integration.
work closely with digital design, analog design, software, back-end, sw and system teams to understand the functional, power and performance goals of the product and ensure its quality.

The Senior Silicon Photonics PIC Design Engineer will help build next-generation Photonic Integrated Circuits (PICs) that power high-performance optical interconnect solutions. In this role, you will lead the design, simulation, layout, and system-level testing of advanced silicon photonics components, while contributing to optical test instrumentation for emerging semiconductor test markets.
As a member of the Silicon Photonics Engineering Staff, you will be a key player in the definition, implementation, and validation of complex automated test equipment that interfaces optical ports of silicon photonic devices at all stages of fabrication, from wafer probe to packaged test.
Lead the design, simulation, layout, and system-level testing of advanced silicon photonics components and Photonic Integrated Circuits.
Utilize simulation and design tools, including Ansys/Lumerical and Cadence Virtuoso, to design, validate, and optimize photonic designs.
Collaborate closely with design, layout, EIC, packaging, validation, quality, and system architecture teams to develop high-performance integrated photonic circuits and validate link performance.
Partner with fab and process engineers to define and optimize device design and implement process monitoring structures.
Develop test and qualification plans in coordination with validation and quality engineering teams.
Conduct rigorous testing and characterization of devices and PICs, including passive and active photonic components.
Engage in direct collaboration with silicon foundries to streamline processes and support successful tape-out execution.

The Senior Silicon Photonics PIC Design Engineer will help build next-generation Photonic Integrated Circuits (PICs) that power high-performance optical interconnect solutions. In this role, you will lead the design, simulation, layout, and system-level testing of advanced silicon photonics components, while contributing to optical test instrumentation for emerging semiconductor test markets.
As a member of the Silicon Photonics Engineering Staff, you will be a key player in the definition, implementation, and validation of complex automated test equipment that interfaces optical ports of silicon photonic devices at all stages of fabrication, from wafer probe to packaged test.
Lead the design, simulation, layout, and system-level testing of advanced silicon photonics components and Photonic Integrated Circuits.
Utilize simulation and design tools, including Ansys/Lumerical and Cadence Virtuoso, to design, validate, and optimize photonic designs.
Collaborate closely with design, layout, EIC, packaging, validation, quality, and system architecture teams to develop high-performance integrated photonic circuits and validate link performance.
Partner with fab and process engineers to define and optimize device design and implement process monitoring structures.
Develop test and qualification plans in coordination with validation and quality engineering teams.
Conduct rigorous testing and characterization of devices and PICs, including passive and active photonic components.
Engage in direct collaboration with silicon foundries to streamline processes and support successful tape-out execution.

You'll be joining our Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You will be leveraging your backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

As the Physical Design Manager, you will provide strategic and technical leadership to a team of engineers, guiding them through the entire chip design lifecycle. You will be responsible for the group's output, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

Review micro-architecture specifications

Supervise verification team members and provide professional guidance

Implement Verification environment UVM based

Collaborate with Design engineers to resolve bugs and achieve coverage closure

Work with the firmware/Lab teams to verify chip flows

Perform debug, root-cause analysis, and post-silicon validation in the lab

Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab

We are looking for an experienced Design Verification engineer to join our DFT team and help establish and grow DFT DV activity in the Cisco SiliconOne DFT team. This role is relevant for engineers with experience in DV roles, either in DFT DV or in other verification domains, who are interested in becoming familiar with DFT design, verification methodologies, and the challenges of validating testability features in advanced silicon.

Your Impact
Lead and drive DFT verification activities within the Cisco SiliconOne DFT team.

Develop verification plans, environments, checkers, assertions, and coverage models for DFT features.

Verify DFT architecture and implementation in close collaboration with DFT, design, architecture, and verification teams.

Work on verification of scan, MBIST, IJTAG/JTAG, test access mechanisms, DFT controllers, and related SoC-level test features.

Debug complex pre-silicon issues across RTL, verification environments, and DFT logic.

Contribute to scalable methodologies, reusable verification components, and best practices for DFT DV.

Help bridge between general DV methodologies and DFT-specific design and verification needs.

As a Project Manager, you will support multiple ASIC development programs by coordinating execution, tracking deliverables, and enabling collaboration across engineering teams. You will strengthen operational excellence through AI-based automation and tracking solutions. Your work will help teams identify risks and dependencies early, maintain alignment, and deliver programs successfully.

Support Program Managers throughout each phase of ASIC program execution.
Track milestones, action items, dependencies, risks, deliverables, status reports, dashboards, and execution metrics across multiple projects.
Coordinate activities among ASIC, Software, and Business Operations teams, including global stakeholders.
Drive follow-up and accountability to ensure project actions are completed on time.
Develop AI-powered tracking tools and automation solutions that improve project visibility, streamline processes, and strengthen program management methodologies.
Collaborate with engineering and operations teams to maintain alignment and support successful program delivery.

In this role, you will contribute to the development of complex ASIC package designs from early planning and exploration through implementation and tapeout. You will collaborate across package design, layout, SI/PI, and silicon teams to help deliver high‑speed, robust, and manufacturable package solutions.

You will participate in package architecture activities, design tradeoff discussions, and technical problem solving while growing your expertise in advanced packaging technologies and system-level integration. This role provides an opportunity to work on some of the most advanced networking silicon products in the industry within a highly collaborative engineering environment.

Responsibilities:
As a member of the Package Design team, you will:

Lead the package design activities including planning, floorplanning, pinout optimization, stack‑up definition, and high‑speed routing support.

Collaborate with SI/PI, silicon floorplanning, layout, and manufacturing teams to ensure high‑quality package solutions.

Support package implementation activities and work closely with layout designers to ensure alignment between design intent and physical implementation.

Participate in technical investigations, design reviews, and tradeoff discussions involving performance, manufacturability, and schedule considerations.

Assist in developing and improving package design methodologies, flows, and best practices.

Contribute to debugging, issue resolution, and package bring‑up activities as needed.

Lead hands-on lab debugging to fix complex silicon performance, characterization, and yield issues. Use bench findings and board-probing data to give feedback directly to the architecture and design teams. Lead ASIC bring-up on validation boards, focusing heavily on SerDes, high-speed interfaces, and power/clock domains. Run characterization across PVT (Process, Voltage, Temperature) conditions and analyse large datasets to resolve performance bottlenecks and improve chip yield. Write and optimize clean Python code to automate lab equipment and test internal chip logic. Serve as the technical lead for complex hardware debug, defining validation methodologies, and advanced lab measurement techniques for the team.

You will work on physical synthesis, place and route, optimization, timing closure, and floor planning activities. Success in this role means delivering high-quality implementation results, learning quickly from senior engineers, and helping improve the flow and methodology used by the team.

Contribute to physical synthesis, place and route, optimization, and timing closure for complex VLSI designs.
Support design floor planning and implementation planning in collaboration with senior physical design engineers.
Analyze timing, congestion, power, area, and design-rule issues and help drive them toward closure.
Work with physical design verification flows, including LVS and DRC, to support clean implementation handoff.
Partner with cross-functional teams to debug implementation issues and improve backend flow quality.

Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab