דרושים » חשמל ואלקטרוניקה » Analog Design Engineer

Required Failure Analysis Engineer
Job Location:
Israel, Hod HaSharon (Hybrid)
Job Brief:
Drive fault isolation and root cause analysis of advanced semiconductor devices, with a focus on memory arrays and associated logic and peripheral circuitry.
Job Description:
Lead fault isolation and root cause analysis of memory and logic failures, including electrical, test, and yield failures, from initial failure signature through physical confirmation
Analyze failures at device, memory-cell, array, and circuit level, differentiating between design, test, device, process, and physical failure mechanisms
Correlate electrical characterization, memory-test and yield results, schematics, layout, and physical FA findings to identify and validate root cause
Develop and execute effective fault-isolation strategies, localizing failures down to the relevant cell, circuit, interconnect, or physical structure
Work closely with Design, Device, Test/Product, Process, Reliability, and Physical FA labs to solve complex failures and drive corrective actions
Improve FA methodologies, prepare and present engineering FA report on complex failure investigations.

We are seeking a highly experienced professional with a strong background in RF, digital, and system-level testing, and with the ability to guide technical decisions, solve complex integration challenges, and support advanced test equipment for production environments.

What will you do:

Design and develop Automated Test Equipment (ATE) for RF, digital, and mixed-signal products at board and system levels.

Lead the technical definition and implementation of test strategies in collaboration with R&D, product engineering, and manufacturing teams.

Own the technical analysis of system schematics, block diagrams, and interface requirements to define robust and reliable ATE solutions.

Support production lines by troubleshooting test failures and optimizing test processes for yield and throughput improvements.

Provide technical guidance for integration with software and firmware control and automation systems.

Evaluate and select test instruments, fixtures, and measurement techniques based on product specifications.

Maintain documentation for test systems, including design files, calibration procedures, and troubleshooting guides.

Mentor engineers and technicians on ATE methodologies, operation, and maintenance.

Required Wafer-Scale System: Computation (LLM) and Communication (NoC) Co-Design
In this job opening, we are seeking a highly motivated and visionary researcher to join our team focused on chiplet-based computing systems. This role involves research and development in chiplet-based architectures, aiming to overcome performance and scalability limits of traditional compute platforms.
Responsibilities:
Conduct cutting-edge research on the co-design of communication and computation for wafer-scale systems. On the communication side, the work focuses on architecting Networks-on-Chip, providing scalable, high-bandwidth, and ultra-low-latency interconnects that efficiently span multiple dies and support fine-grained data movement. On the computation side, the research emphasizes optimizing and mapping training and inference workloads to fully exploit wafer-scale resources, improving performance, scalability, and energy efficiency through intelligent task placement and scheduling.
Investigate various aspects of system design, including:
Network-on-Chip design, further including Topology exploration, routing algorithms, and protocol/flow-control design to support high-throughput collective communication, low-latency synchronization, and efficient model/data parallelism
Expressing and Mapping LLM Parallelism to Wafer-Scale System that simplify LLM parallelism (e.g., tensor, pipeline, and data parallelism) and efficiently map training and inference workloads onto wafer-scale system.

We are looking for a highly analytical, detail-oriented Innovation Expert to join our Open Innovation team. This role is ideal for candidates who sit at the intersection of deep tech, startup ecosystem and academy, possessing strong technology analytical skills, clear communication, and a foundational background in computer architecture research.
In this role, you will drive our external innovation strategy by managing academic research collaborations, scouting early-stage deep-tech startups and conducting technical due diligence.
Key Responsibilities:
Academic Cooperation & Research Partnerships: Identify and build direct collaboration agreements with world-class professors, research labs, and universities. Facilitate joint research projects, tech-transfer initiatives, and track academic spin-offs.
Startup Scouting & Ecosystem Mapping: Actively identify, source, and map early-stage deep-tech startups and emerging tech companies globally within the companys strategic domains.
Technical Due Diligence: Evaluate startup technologies, product-market fit, and team capabilities. Analyze technical validity and assess how external innovations align with our internal roadmaps.
Ecosystem Analysis: Conduct deep-dive analyses of startup ecosystems, venture capital trends, and academic spin-offs to identify high-potential investment and collaboration opportunities.
Investment & Collaboration Support: Synthesize technical and commercial findings into clear, structured scouting reports, investment tech memos, and presentations for senior leadership to drive partnership or investment decisions.
Cross-Border Collaboration: Act as a bridge between startup founders, academic innovators, and internal global teams (including European and China-based business units) to facilitate joint POCs, or investment reviews.
Track Tech Domains: AI infrastructure, advanced semiconductors, hardware-software co-design, and AI data movement.

Required CPU Core Micro Architect
Job Description
Our goal is to design cutting-edge CPUs for smartphones, servers, and desktops, and we need the very best talent to help us achieve it!
The CPU Micro architect will take charge in defining a processor Micro architecture features that will improve the performance and reduce the power consumption of the CPU core. This architect will use a performance simulator to explore his ideas and will analyze implementability of these features: Power, Timing, Area. This architect will utilize his processor and VLSI design experience to develop many advanced features for Huawei processors.