דרושים » חומרה » FPGA Engineer

We are looking for experienced FPGA Engineers to lead innovation in the next generation space connectivity technology.
What you will be doing​:
Design and manufacture systems including ICs by RS and SoC type FPGAs
Design and implement high-speed digital signal processing algorithms.
Design for highly robust, distributed systems with emphasis on managing physical effects that originate from the harsh space environment.
Implement DSP algorithm on SoC type FPGAs.
Key contributor to Digital, Modem architecture and design.
Lead technical reviews with key stakeholders.
Work closely within a multi-disciplinary team to lead high-impact technical decisions about system design, implementation, and verification.

As a key member of our team, you will be responsible for the selection, development, and seamless integration of FPGAs that implement critical functionality on our prototypes. Your work will span a wide range of applications, from crafting low-level hardware control and status for embedded systems and high-speed links, to integrating high-level IP blocks and developing custom hardware-accelerated algorithms and filters. You will leverage your strong foundation in digital design and communications, working with micro-controllers, microprocessors (ARM), and various peripheral interfaces (I2C, SPI, high-speed serial interfaces), and industry-standard protocols (PCI Express, USB, Ethernet). This role requires significant hands-on experience with board bring-up and debug of complex digital hardware.

FPGA Verification engineer (6160) We are seeking a talented and experienced FPGA Verification engineer to join our hardware development team. In this role, you will be responsible for defining and executing comprehensive verification strategies for complex FPGA-based systems, from architectural definition through system integration.

We are seeking a skilled Digital Hardware & FPGA Engineer. Role Overview: Lead development of FPGA components in Embedded systems and advanced hardware infrastructures.

we're seeking a talented Senior ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects.

As a Senior ASIC Design Engineer, you won't just build chips-you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Design Ownership & Implementation

Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support
Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions
Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams
Quality Assurance & Design Optimization

Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient
Apply design techniques to meet PPA (Power, Performance, Area) targets
Contribute to design quality through verification and validation activities
Methodology Innovation & Collaboration

Participate in design methodology improvements and tool automation initiatives
Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter
Collaborate effectively across teams to ensure seamless integration

This role has been designed as Hybrid with an expectation that you will work on average 2 days per week from our office.

Roles and Responsibilities:
Design, develop, and enhance I/O subsystems, virtualization, kernel programming, and memory management for cutting-edge system software products.
Drive performance optimization, and efficient memory management.
Perform in-depth debugging, triaging, and resolution of user and kernel-level, performance profiling, and memory-related issues.
Develop innovative solutions, addressing challenges in virtualization, multithreading, and hardware-software interaction.
Explore and implement new methodologies fostering continuous improvement and innovation.
Proactively identify bottlenecks in system design, and recommend and implement robust, scalable solutions.
Stay updated on evolving trends in kernel development, design, and virtualization technologies to bring innovative practices to the team.
Troubleshoot and optimize complex I/O and kernel features to enhance performance, scalability, and reliability.
Collaborate with cross-functional teams to align on design goals and ensure seamless integration with the system architecture.
Exhibit flexibility in taking on new or related tasks, showcasing adaptability and a proactive, problem-solving mindset.
Provide technical leadership in architecture design, problem-solving, and decision-making across complex technical domains.
Lead technical discussions, design reviews, and decisions on critical system challenges, driving the adoption of innovative solutions and best practices.

Our team in Israel is looking for a Senior Hardware Validation Engineer Hardware Test Engineer to join the board design Hardware Team.
The team leads the development of networking infrastructure for our next-generation data centers, focusing on accelerated performance and optimized end-to-end GPU connectivity.
We are looking for a hands-on and detail-oriented Practical engineer with strong lab skills, who enjoys working in a dynamic, multidisciplinary environment.
What youll be doing:
Perform board bring-up, validation, and debugging activities in the lab
Operate lab equipment such as oscilloscopes, power supplies, logic/spectrum analyzers, and multimeters
Support hardware investigations by reading schematics, analyzing layouts, and completing test procedures
Document test results and communicate findings clearly to engineering teams
Work closely with electrical, mechanical, thermal, and system engineers throughout the development cycle.

we're seeking a highly skilled Physical Design CAD Engineer specializing in CAD Extraction to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the parasitic extraction (PEX) methodologies and flows for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the accuracy and efficiency of our extraction environment, ensuring that our high-speed designs are modeled with the highest precision from RTL to GDSII.

Key Responsibilities

Develop, qualify, and maintain automated RC extraction flows for high-performance AI SoCs
Own the setup and validation of foundry technology files (e.g., StarRC/Quantus techfiles, TLU+, ITF) across various process corners
Perform correlation studies between different extraction tools and 3D field solvers (e.g., Raphael, QuickCap) to ensure modeling accuracy
Collaborate closely with the Signal Integrity (SI) and Power Integrity (PI) teams to provide accurate parasitic data for critical high-speed nets and power grids
Implement automated scripts (Tcl/Python) to streamline extraction regressions, data parsing, and PEX-to-STA (Static Timing Analysis) handoffs
Analyze the impact of layout effects (LDE) and parasitics on timing and power, providing feedback to the implementation team to optimize PPA
Interface with EDA vendors and foundries to resolve extraction tool bugs and methodology gaps related to advanced nodes (5nm/3nm)