לוח משרות דרושים FPGA

Requirements:
7+ years of experience in ASIC/FPGA verification.
- Leading skills to drive a team of 3-4 engineers.
Strong System-Verilog experience
Familiarity with simulation tools/environments, verification methodologies
Strong team player, solid interpersonal skills
Entrepreneurial can-do attitude, self-motivated, able to work independently
BS/MS in EE/CE from leading universities
Background in one or more of the following domains is an advantage:
- Ethernet
Using/implementing UVM/OVM testbench.
Familiarity with a verification of DSP blocks
Verification using main bus protocols (AMBA/interconnect/etc.)
Scripting experience using the following: Python, Perl

Requirements:
Required BSC EE-engineer/Computer-science from a leading institute with excellence 10+ years experience in micro-architecture and RTL design in FPGA/ASIC 5+ years experience in managing a FPGA team Experience in managing complex FPGA projects, which include complex design blocks. Deep understanding in FPGA internal structure, interconnects, interfaces, high frequencies Advantage.
Knowledge in Altera FPGAs Knowledge in PCIe Knowledge in DDR. Knowledge in packet processing and networking blocks.

Requirements:
5 years of experience.
Experience with video algorithms.
Experience with Xilinx Proficiency in VHDL
Ability to understand electronic schematics.
System overview capabilities.
Knowledge in high-speed interfaces advantage.
Experience with DDR and embedded systems.
Strong simulation knowledge

Requirements:
B.Sc./M.Sc. in Electrical Engineering 3+ years of experience in FPGA development (Xilinx) Experience with Xilinx flow and tools (Viv ado,SDK) Experience with FPGA coding (Verilog preferred), synthesis, place and route, timing analysis and timing closure. Experience with writing advanced Test Bench Experience with simulation Experience with lab FPGA debug (Signal Tap and Chip scope) Experience with lab testing equipment for communication systems Excellent collaboration and communications skills

Advantages: Knowledge of networking and communication standards Experience with advanced verification methodologies using System Verilog (coverage driven and direct tests) Experience with Python Knowledge in UVM Knowledge in board design.

Requirements:
At least BSc in Electrical Engineering.
At least 5 years of experience with large FPGA development on Altera or Xilinx devices.
Hands on with lab FPGA debug methodologies, such as ChipScope or SignalTap.
Background in communication algorithms.
Preferably - experience in team management.
Self-learning and problem-solving skills.

Requirements:
* BSc or MSc or equivalent experience in electrical engineering.
* At least 3-4 years of relevant experience (as an architect).
* Rich experience in RTL design (for FPGAs/ASICs, using VHDL/Verilog/System Verilog)
* Hands-on experience with synchronous and high performance pipeline architecture A must
* Be able to take an algorithm, function or behavior and to generate an architecture out of it to be implemented on FPGA or ASIC.
* Deep understanding of how to build and integrate system with various technology components.
* Deep understanding of how a block should be implemented.
* Understanding of the relationship between HW and SW.
* See the overall system and full picture.
* High skills on writing documents and drawing diagrams.
* Attention to details on design and high focus on design quality.
* Knows to do tradeoffs.
* Experience with IP integration (ARM, AXI bus, Ethernet MAC etc.).
* Familiarity with Xilinx/ALTERA/Lattice FPGA architecture.
* High energy with leadership and excellent interpersonal skills and possess ability to learn complex concepts in a fast pace environment.
* Experience with board design preferred
* Experience with safety-critical systems preferred
* Experience with automotive systems preferred.

Requirements:
To perform this job successfully, an individual must be able to perform each essential duty satisfactorily
* Bachelors degree in Electrical Engineering, Software Engineering or Computer Science
*  Engineering background
* Demonstrated experience in designing complex designs including coding, Verification synthesis and integration of 3rd party IPs
* 7+ years of experience as hands-on with FPGA/ASIC development
* Experience in leading a team of chip designers an advantage
* Team player with good oral and written communication skills.
* Ability to quickly learn new skills, adapt to change and enter new technical fields
* Experience with VHDL/Verilog (System Verilog Advantage)
* Hands-on experience with synchronous and high-performance pipeline architecture
* Good understanding of Ethernet, Networking, Microprocessors an advantage
* Familiarity with Xilinx/ALTERA/Lattice FPGA architecture
* Excellent communication skills with fluent verbal and written English.