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חברה חסויה
Location: Haifa
Job Type: Full Time
Required Senior IC Test Engineer
Haifa
Full time
We are the Production Test team - responsible for the definition, development, and deployment of production test operations for the worlds most advanced SoCs for ADAS and self-driving vehicles.
This is your opportunity to join a team during its initial forming stage and leave your mark as we assume full ownership for its silicon production operations to enable high volume manufacturing for cutting-edge automotive products.
What will your job look like?
Work closely with the design teams from early stages of the design process to review DFX architecture and define test requirements.
Define test methodologies and generate test content for high-speed interfaces of embedded IP blocks (LPDDR4/5, PCIe Gen4/5, D/C/MPHY).
Test program coding, pattern conversion and pre-Si validation (virtual test simulations)
Support Load Board and Probe Card design activities.
Lead post-Si test program debug activities to enable delivery of samples to internal and external customers.
Test program characterization and tuning to enhance test program quality to meet automotive standards.
Support Quality & Reliability team to enable effective and timely qual plan execution.
Lead test deployment activities with tier-one Foundry and OSAT vendors to enable large-scale Wafer-Sort and Final-Test operations.
Requirements:
BSc or MSc degree in Electrical Engineering.
7+ years of experience as IC Product/Test engineer.
Hands on experience in bring-up & productization of complex IC products.
Prior experience with Teradyne UltraFlex/UltraFlexPlus is - significant advantage.
Deep understanding of structural DFT methods (scan, mbist, jtag, ).
Proficiency in C/C++ and scripting language (Perl, Python, ) in Unix environment.
Experience with data and yield analysis using known statistical methods and tools (e.g. JMP).
Familiarity with Verilog and RTL behavioral simulations - an advantage
Strong sense of ownership, commitment, and responsibility.
Team player, with the ability to work in a rapidly evolving environment.
Good interpersonal communication skills.
This position is open to all candidates.
 
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01/04/2026
חברה חסויה
Location: Haifa
Job Type: Full Time
As a Senior DFT Engineer at Astera Labs, you will be at the intersection of architecture, design, and production. You won't just run tools-you will be a foundational member of the team responsible for the entire lifecycle of our silicon's reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable. If you thrive on solving complex challenges in deep-submicron processes and want to establish world-class DFT methodologies, this is your opportunity.

Key Responsibilities

DFT Architecture & Strategy

Own the DFT journey from high-level architecture definition and RTL design to backend implementation and post-production support
Develop comprehensive Design-for-Testability (DFT) strategies for next-generation connectivity platforms, ensuring chips meet the highest quality standards
Define DFT architectures including JTAG/iJTAG, MBIST, Scan, and ATPG methodologies
Test Pattern Development & Optimization

Generate and optimize high-quality test and debug patterns for production
Perform Static Timing Analysis (STA) for DFT modes and conduct gate-level simulations to ensure robust performance
Drive test coverage and quality metrics to meet stringent manufacturing requirements
Cross-Functional Collaboration & Methodology Innovation

Act as a multidisciplinary bridge, collaborating closely with Architecture, Verification, and Backend teams to ensure seamless integration and optimal QoR
Participate in developing and maintaining cutting-edge DFT implementation flows
Automate and improve methodologies using advanced scripting and tools
Requirements:
Bachelor's degree in Electrical Engineering or related technical field
3+ years of hands-on experience in DFT roles at semiconductor companies
Deep expertise in DFT flows and architectures including JTAG/iJTAG, MBIST, Scan, and ATPG
Proficiency with industry-standard EDA tools from Synopsys (TestMAX) or Mentor (Tessent)
Strong understanding of logic design, verification, debug, and Static Timing Analysis (STA)
Scripting proficiency in Tcl, Perl, Python, or Shell for automation and innovation
This position is open to all candidates.
 
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27/04/2026
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
As a member of the UC organization, youll support the development and management of Compute, Database, Storage, Internet of Things (IoT), Platform, and Productivity Apps services in our company, including support for customers who require specialized security solutions for their cloud services.

Take part in the development of cutting-edge products within a disruptive system architecture. You will have the opportunity to work on the technologies that power the worlds largest cloud provider, in a dynamic, open, and fast-paced environment. We provide a highly reliable, scalable, low-cost infrastructure platform in the cloud, which powers hundreds of thousands of businesses in 190 countries around the world. Annapurna Labs, as part of us, is looking for talented engineers to help us develop a semiconductor platform based on a revolutionary architecture.

Looking for exceptional senior engineers to join the top-tier team that is developing the next generation semiconductor platform, based on a revolutionary architecture. Engineers will participate in design activities, working on the next generation of our products.

You are invited to take part in developing, integrating and deploying cutting-edge technologies, starting with identification and definition of project requirements, architecture, feature development, and collaboration with the different groups.
Your design will be integrated into the nitro SoC, on millions of servers worldwide. This is an opportunity to have a large-scale impact.
As a VLSI engineer and a member of the Nitro project, you will have an impact over the device through its entire lifecycle, from the product definition stage to mass production. You will work in close collaboration with multiple groups, including Architecture, Software, Verification, Backend, and DFT.

Key job responsibilities
*Full ownership of one or more IPs within the product:
-Micro-architecture.
-RTL coding and debug.
-Synthesis and timing closure.
-Sign-off.
* Supporting the Verification and Emulation teams: Test plan, Coverage review.
* Ensuring that the chip meets quality and reliability standards.
* Collaborating with cross-functional teams, including Product Definition, Verification, Software, and Physical design.
Requirements:
Basic Qualifications
- 6+ years of experience in chip design.
- Hands-on experience in micro-architecture and RTL design (Verilog / System Verilog).
- Scripting expertise in C*, Perl, Python, or TCL.
- BSc in Computer/Electrical Engineering.
- Strong communication and collaboration skills.
- Strong leadership skills and ability to own complex units.

Preferred Qualifications
- Strong knowledge of protocols (AXI, CHI, DDR, Networking, PCIe).
- Experience with Network-on-Chip (NOC) architecture.
- knowledge with coherent and non-coherent fabric design.
- Comprehensive SoC development cycle expertise (Synthesis, STA, CDC, Lint).
- Knowledge of Design Automation tools and techniques.
- Advanced degree in related technical field.
This position is open to all candidates.
 
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חברה חסויה
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior Silicon DFT Lead
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As the Design for Test (DFT) Engineer Lead, you will play a crucial role in DFT Architecture and DFT design, and support devices to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality throughout the project life-cycle, and providing sign-off DFT to tapeout.
Responsibilities
Lead and execute DFT activities in the design, implementation, and verification solutions for Application-Specific Integrated Circuits (ASIC).
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage a DFT team planning, deliverables, and provide technical mentoring and guidance.
Lead DFT execution of a silicon project, planning, execution, tracking, quality, and signoff.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
8 years of experience in Design For Test from DFT architecture to post silicon production support.
4 years of experience with people management.
Experience with DFT design and verification for multiple projects, DFT specification, definition, architecture, and insertion.
Experience with DFT techniques and common industry tools, DFT and Physical Design flows, and DFT verification flow.
Experience in leading DFT activities throughout the whole ASIC development flow.
Preferred qualifications:
Master's degree in Electrical Engineering or a related field.
Experience in post-silicon Debug, test or product engineering.
Experience in Joint Test Action Group (JTAG) and Internal JTAG (iJTAG) protocols and architectures.
Experience in SoC cycles, silicon bring-up, and silicon debug activities.
Knowledge of fault modeling techniques.
This position is open to all candidates.
 
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לפני 1 שעות
חברה חסויה
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior SOC DFT Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will play a crucial role in Design for Testing (DFT) Architecture and DFT design, and support devices of extreme complexity to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality matrix throughout the project life-cycle, and providing sign-off DFT to tapeout.
Responsibilities
Lead and execute activities in the design, implementation, and verification of DFT solutions for large-scale ASICs.
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage the DFT team's workload and deliverables, provide technical leadership and guidance to the team.
Lead DFT execution of a silicon project (e.g., planning, execution, tracking, quality, and signoff).
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
8 years of experience in Automatic Test Pattern Generation (ATPG) methods.
Experience with multiple projects in DFT design and verification, DFT specification, definition, architecture, and insertion.
Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow.
Experience in leading DFT activities throughout an ASIC development flow.
Preferred qualifications:
Master's degree in Electrical Engineering or a related field.
Experience in JTAG and iJTAG protocols and architectures.
Experience in post-silicon test or product engineering.
Experience in SoC cycles, silicon bring-up, and silicon debug activities.
Knowledge of fault modeling techniques.
This position is open to all candidates.
 
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Location: Haifa
Job Type: Full Time
The V&V Lead will also support product development activities as a Test Engineer by designing and implementing detailed, comprehensive, well-structured test plans and test procedures.
The V&V Lead will need to have people management experience, as well as technical experience, including instrumentation, medical device V&V, and test method validation.
The V&V Lead should be creative and proactive to work successfully in a fast-paced environment, contributing to early prototype evaluations, test method development, design feedback to engineering teams, defect identification, and troubleshooting.



This is a full-time, exempt position located in our Haifa, Israel office and reports to the Verification and Validation Manager.



ESSENTIAL DUTIES AND RESPONSIBILITIES:

Line manager to Israel-based V&V Test Engineers and V&V Test Technicians for design verification activities.
Contribute to continuous improvements of the quality system and V&V process as part of the integrated V&V team across multiple locations.
Lead a team of different role types and varying levels of experience to perform the design V&V activities in support of product development activities.
Engage with leadership and cross-functional peers to ensure the design V&V team is integrated into the product development process, meeting both product quality and milestones on time.
Coordinate V&V activities of product development and sustaining projects.
Serve as signature alternate for V&V Manager on project-level documents, when appointed.
Execute V&V engineering work as an individual contributor when needed:
Plan test strategy and establish clear traceability between requirements and test procedures.
Analyze requirements and write test procedures with robust coverage of requirements using different test scenarios.
Write instruction-based test procedures and design test fixtures and/or SW tools as needed.
Guide and participate in the review of team members work output (above bullets) as needed to ensure a consistent quality level.
Train V&V team members on the quality system and V&V process.
Requirements:
B.S. Degree in Engineering or other technical discipline; OR Secondary school diploma, plus relevant work experience




Knowledge:

At least 5 years of medical or related industry experience in product development and/or testing.
V&V for medical device experience is preferred, or V&V in a related field with similar controls.
At least 2 years of management or leadership experience / Proven ability to manage a V&V team.
Strong verbal and written communication skills in English, including ability to give clear direction to team members.
Experience in designing, writing, reviewing, and performing design verification tests .
Experience organizing and planning test efforts.
Experience designing and creating test fixtures.
Experience in medical device product development preferred.
Familiarity with measurement uncertainty analysis and test method validation.
Demonstrated technical writing skills.
Strong grasp of fundamental engineering concepts, basic principles.
Critical thinking and decision making, including the ability to recognize when to ask questions.
Highly organized and strong attention to detail.
Capable working in a multi-disciplinary environment involving software, hardware, and mechanical engineers.
Able to work in a team environment and execute responsibilities with minimal direct supervision.
This position is open to all candidates.
 
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לפני 10 דקות
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Rק/וןרקג Power and Signal Integrity Engineer, PhD Graduate
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Power and Signal Integrity Engineer, you will be responsible for the design and characterization of signal and power integrity of our IC designs. You will design the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives and set up methodologies, perform simulations, silicon characterization and correlations to ensure our IC designs meet systems design budgets and achieve the highest performance. You will work with systems architects, ASIC design, systems engineers, and partner cross-functionally with teams and external vendors/partners.
Responsibilities
Generate precise electrical models (e.g., S-parameters, SPICE models) for components such as packages, PCBs, and connectors for use in simulations.
Simulate high speed interface electrical behavior using HSPICE or other circuit simulators.
Execute lab measurements utilizing test equipment like oscilloscopes, Vector Network Analyzers (VNA), Time Domain Reflectometers (TDR), spectrum analyzers to validate simulation outcomes and debug signal and power-related issues on silicon prototypes and boards.
Establish design rules and guidelines for optimal signal/power integrity during PCB and package layout, ensuring high production yield and reliability.
Document design specifications, analysis results, and validation reports to ensure compliance with standards and for future reference, while collaborating extensively with cross-functional teams, including ASIC architects, digital/analog designers, physical design/layout engineers, and system engineers.
Requirements:
Minimum qualifications:
PhD degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.
Experience in any signal and power integrity domain of electrical engineering through internships, academic research, or publications.
Preferred qualifications:
Experience with industry-standard Electronic Design Automation (EDA) tools for simulation and layout (e.g., Cadence Sigrity/Allegro, Ansys HFSS/PowerDC/Q3D, Keysight ADS, Synopsys HSPICE).
Experience with signal and power integrity modeling and simulation for high-speed interfaces (e.g., LPDDR, MIPI, UFS, PCIe, USB).
Experience with SerDes testing in a lab setting, and familiarity with Ethernet, PCIE, and DDR standards.
Experience in scripting languages such as Python, Perl, or Tcl for flow automation and data analysis.
Familiarity with high-speed testing equipment like VNAs, TDRs, and oscilloscopes for measurement and validation.
Knowledge of circuit analysis, electromagnetics, and transmission line theory.
This position is open to all candidates.
 
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01/04/2026
Location: Haifa
Job Type: Full Time
As a Package Design Engineer, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon. You will execute the package flow, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners. You will be responsible for implementing package technologies that meet aggressive electrical, thermal, mechanical, and cost targets, enabling products to operate reliably in the worlds most demanding AI and cloud environments.

Key Responsibilities


Execute end-to-end IC package design, from early feasibility and detailed design through to qualification and high-volume manufacturing
Implement package architecture and utilize advanced technologies (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration)
Drive signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices
Perform package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and apply mechanical constraints
Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance
Interface directly with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets are met
Conduct package-related risk assessments, failure analysis, and corrective actions during bring-up and production ramp
Support NPI, qualification, and product sustainment activities, including vendor technical reviews
Requirements:
5+ years of hands-on IC package design experience for high-performance semiconductor products, with full technical ownership from concept through tape-out
Expert proficiency in IC package design tools (Cadence APD / SiP or equivalent) and hands-on experience designing complex packages (BGA, FCBGA, FCCSP)
Strong package integration expertise, including stack-ups, ball/bump maps, constraints, SMT integration, and package BOM ownership
Deep understanding of signal, power, and thermal integrity at the package level, with the ability to execute design tradeoffs based on analysis
Proven manufacturing and release experience, including running DRC/LVS/DFM, OSAT engagement, and delivering production-ready package designs
This position is open to all candidates.
 
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לפני 24 דקות
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Power and Signal Integrity Engineer
About the job
As a Power and Signal Integrity Engineer, you will be responsible for the design and characterization of signal and power integrity of our IC designs. You will design the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives.
You'll set up methodologies, perform simulations, silicon characterization and correlations to ensure our IC designs meet systems design budgets and achieve the highest performance. You will work with systems architects, ASIC design, systems engineers, and partner cross-functionally with teams and external vendors/partners.
Responsibilities
Design and optimize power distribution networks (PDN) across chip, package, and board levels. This includes managing power/ground planes, decoupling capacitors, and power gating strategies.
Conduct both pre-layout and post-layout power integrity simulations to analyze power and ground noise (SSN/SSO), voltage drops (IR drop), and electromagnetic interference (EMI).
Implement and verify low-power design methodologies, such as multi-voltage designs and clock gating, using power intent formats like UPF/CPF.
Generate precise electrical models (e.g., S-parameters, SPICE models) for components such as packages, PCBs, and connectors for use in simulations.
Execute lab measurements utilizing test equipment like oscilloscopes, Vector Network Analyzers (VNA), Time Domain Reflectometers (TDR), Spectrum analyzers to validate simulation outcomes and debug signal and power-related issues on silicon prototypes and boards.
Requirements:
Minimum qualifications:
Bachelor's degree in Mechanical, Electrical Engineering, Material Science, or equivalent practical experience.
5 years of experience in signal or power integrity or hardware design.
Preferred qualifications:
Experience with industry-standard Electronic Design Automation (EDA) tools for simulation and layout (e.g., Cadence Sigrity/Allegro, Ansys HFSS/PowerDC/Q3D, Keysight ADS, Synopsys HSPICE).
Proficiency in scripting languages such as Python, Perl, or Tcl for flow automation and data analysis.
Familiarity with high-speed testing equipment like VNAs, TDRs, and oscilloscopes for measurement and validation.
Knowledge of circuit analysis, electromagnetics, and trans
This position is open to all candidates.
 
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Location: Haifa
Job Type: Full Time
Required Experienced SoC Verification Engineer
Haifa
Full time
Our SOC verification group owns the important and challenging job of verifying our chip. It is involved from product specification to final SOC delivery, and involves all the system components. The group is made up of few of the best verification engineers, so besides contributing to making our roads safer, youll get the chance to work at one of the most professional verification teams.
What will your job look like:
You'll be responsible for Pre-Silicon system-level verification of the most cutting-edge AI accelerators and technologies in the automotive field.
Define the TestPlan, develop and run tests on simulation/emulation environments, develop test environment and verification collaterals.
You'll have a broad effect on our unique product from the very beginning of the process.
Requirements:
BSc in electrical engineering, computer engineering or computer science
7+ years of experience working in verification environment, tests, and test bench development (C/C++/SV)
TestPlan defining and Coverage-Driven Verification experience
Fullchip/SOC verification experience, strong system understanding
Good debug capabilities using the latest EDA tools
Knowledge in Industry Standard protocols such as AXI/ACEL/OCP/CHI
SW embedded experience, C/C++ skills - Advantage
Strong skills in scripting Perl/Python - Advantage
System Verilog writing skills, preferably in OVM/UVM - Advantage
3rd-party IPs integration testing experience - Advantage.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8637733
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חברה חסויה
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
As a Design Verification Engineer, you will be responsible for ensuring "bug-free first silicon" for complex IP and SoC designs. You will drive all phases of pre-silicon verification, from defining methodologies and test plans to RTL freeze and tape-out sign-off. These roles are highly collaborative, requiring close interaction with architecture, design, and software teams across global sites.
Responsibilities
Architect and develop scalable, portable verification environments, including UVM-based testbenches, protocol monitors, agents, and checkers.
Define detailed test and coverage plans based on micro-architecture specifications and extract features for DV attributes.
Create and simulate test scenarios, perform advanced debugging, and conduct end-to-end simulations of data/control paths.
Drive regression and coverage analysis (metric-driven verification) to ensure the highest quality, productivity, and time-to-market.
Partner with architects and designers from the early stages of feature definition to influence IP/SoC specifications.
Apply formal verification, hardware acceleration, and power/performance (NLP) analysis where applicable.
Requirements:
Ranges from 2+ to 7+ years in digital logic design verification (IP or SoC level).
B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or Computer Science.
Expert-level knowledge of SystemVerilog and UVM (or high-level C/C++ in lieu of UVM for specific teams).
Proficiency in Python, Perl, or TCL for automation and tool development.
Extensive experience with simulators, waveform viewers, and coverage collection tools.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8607806
סגור
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