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לפני 13 שעות
חברה חסויה
Location: Caesarea
Job Type: Full Time
We are looking for a highly motivated and experienced Senior Verification Engineer to perform and guide design verification for the electro-mechanical portions of the system design.
For this role, were focusing on electrical and mechanical parts, assembly and functional aspects of the system design. This is an ideal opportunity for someone who is motivated and passionate to make an impact in leading the development of the next generation of ophthalmic robotic surgery.
Responsibilities
Create verification protocols based on electromechanical design input requirements.
Identify applicable standards for each electromechanical aspect and define how they are addressed in verification activities.
Establish statistical sample sizes according to the risk level associated with each part, assembly, and feature.
Lead protocol development and test execution for sterilization validation.
Guide a team of verification engineers and testers in creating test protocols, executing tests, reviewing results, and generating reports.
Participate as a team member in the development of new features related to electromechanical assemblies and associated robotic capabilities.
Requirements:
BSc degree in Electrical or Mechanical, or Biomedical Engineering.
5+ years of experience in design verification of electrical, mechanical, and multi-disciplinary medical device systems.
Experience with optical systems (e.g., imaging, illumination, lenses, cameras) in medical devices - an advantage.
Proven experience in establishing and justifying statistical sample sizes for verification activities.
Experience with sterilization processes and validation - an advantage.
Familiarity with medical device standards and regulations, such as ISO 13485 and IEC 60601.
Excellent verbal and written communication skills in English.
Strong problem-solving abilities, attention to detail, and the ability to quickly learn new technologies and systems.
This position is open to all candidates.
 
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Location: Caesarea
Job Type: Full Time
We are looking for a talented and experienced engineer to take part in the verification efforts for the companys core product. This position involves building and maintaining a complex verification environment, and defining and executing a test plan. In this role, you will be leading all aspects of verification and will have a critical impact on the company's R&D path.
Responsibilities
Define and implement robust SV/UVM verification solutions, including test benches and methodologies, to drive efficient verification closure across block-level and full-chip designs, integrating Mix-signals SoC simulation environment using Verilog, MATLAB, HW/SW Co-simulation and lab integration.
Work closely with Digital Design, Analog Design, Software, Back-end, SW and System teams to understand the functional, power and performance goals of the product and ensure its quality.
Requirements:
Electrical Engineering B.Sc., Computer Engineering or other relevant engineering department graduate with high scores, or equivalent experience.
5+ years in design verification, with strong SV/UVM proficiency (Less experienced engineers with high university grades or vast knowledge in RTL design will also be considered)
Self-motivated, ability to work, lead and drive tasks to completion.
Great interpersonal skills.
Understanding of digital ASIC design flows and SoC development methodologies. experience with SoC/full-chip verification, simulation/debug tools, and Unix/Linux environments, scripting languages (Python, etc.) and version control.
Advantages
Knowledge in Low Power technics and UPF standard.
Knowledge with Mix signals SoCs.
Knowledge with SW/HW Co-development.
This position is open to all candidates.
 
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חברה חסויה
Location: Caesarea
Job Type: Full Time
We are looking for a talented and experienced engineer to take part in the verification efforts for the companys core product. This position involves building and maintaining a complex verification environment, and defining and executing a test plan. In this role, you will be leading all aspects of verification and will have a critical impact on the company's R&D path.
Responsibilities
Lead the full verification lifecycle and methodologies. Plan, Design and Execute verification of SV/UVM Block level and Full chip environments , creating and execution test plans, tracking progress, and ensuring verification closure across diverse Mix-signals SoC simulation using Verilog, MATLAB, HW/SW Co-simulation and lab integration.
Work closely with Digital Design, Analog Design, Software, Back-end, SW and System teams to understand the functional, power and performance goals of the product and ensure its quality.
Requirements:
Electrical Engineering B.Sc., Computer Engineering or other relevant engineering department graduate with high scores, or equivalent experience.
5+ years in design verification, with strong SV/UVM proficiency (Less experienced engineers with high university grades or vast knowledge in RTL design will also be considered)
Self-motivated, ability to work, lead and drive tasks to completion.
Great interpersonal skills.
Understanding of digital ASIC design flows and SoC development methodologies. experience with SoC/full-chip verification, simulation/debug tools, and Unix/Linux environments, scripting languages (Python, etc.) and version control.
Advantages
2+ years of managerial experience. (Only for DV lead)
Knowledge in Low Power technics and UPF standard.
Knowledge with Mix signals SoCs.
Knowledge with SW/HW Co-development.
This position is open to all candidates.
 
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12/01/2026
Location: Caesarea
Job Type: Full Time and Temporary
Innovation starts from the heart. At our company, we put patients first. We invest a significant proportion of our revenue towards research and development to drive and develop groundbreaking medical innovations for structural heart disease. As part of our R&D Engineering team, you will work closely with our Quality and Manufacturing teams to develop the latest tools and technologies to address significant, unmet clinical needs that impact patients lives around the world.
we are looking for a System Integration Engineer to join our Innovation Center in Caesarea, Israel. In this role, you will lead the integration of sensors (ECG, Bioimpedance) into a heart valve system (delivery and implant). The role includes managing the tasks of 2-3 team members and 1-2 sub-contractors, leading the technical aspects of the mechanical, software, hardware and algorithm development, coordinating tasks to achieve R&D milestones, present project plans, value propositions and demonstrate feasibility to leadership while driving alignment with cross functional teams.
How youll make an impact:
Manage a project with a small team of engineers (3-5 people, no direct reports)
Deliver the R&D plan with needed adjustments
Lead design activities including brainstorming, conceptual design, feasibility testing and VoC.
Collaborate with cross functional teams (marketing, US based R&D).
Develop testing models to prove design theories and validate them.
Lead proof of concept development work including animal trials, in-vitro testing and supporting analyses.
Manage subcontractors in the fields of SW, HW and algorithm development.
Requirements:
B.Sc. in biomedical/electrical engineering.
At least 5 years of experience in R&D.
Analytical thinking and good planning abilities.
Project management or system level engineering experience.
Good understanding of SW/HW.
Proficiency in Python and MATLAB, and familiarity with Agile project management tools such as Jira.
This position is open to all candidates.
 
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חברה חסויה
Location: Caesarea
Job Type: Full Time
Required Logic Design Engineer
Responsibilities
Design and implement complex digital circuits for ultra low-power SoC.
Participate in all phases of SoC design, from specification to coding, debug and tape-out.
Perform RTL design, synthesis, and timing analysis.
Optimize designs for power, performance, and area (PPA).
Collaborate with cross-functional teams, including architecture, System, Software, Analog, verification, and physical design engineers.
Contribute to the development of design methodologies and best practices.
Debug and resolve design issues.
Support Lab bring ups, debug and other activities.
Requirements:
Bachelor's Or Master's degree in Electrical Engineering, Computer Engineering, or a related field
Minimum 5 years of experience in logic design, working in both IP and SOC environments
Proficiency in Verilog or SystemVerilog for design
Experience with industry-standard EDA tools (Synopsys VC, Cadence etc)
Knowledge in low power design techniques
Knowledge of RTL synthesis and timing analysis flows
Strong communication and teamwork abilities
Excellent problem-solving and debugging skills
Advantage
Experience with Analog ICs, Mix-signals design, and Lab equipment
Experience with RISC-V based SoC and FW.
This position is open to all candidates.
 
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31/12/2025
Location: Caesarea
Job Type: Full Time
We are seeking a full-time, on-site Validation engineer to lead automation and manual testing efforts across our product line. This role encompasses validation, functional verification, and Quality Assurance activities for medical devices integrated with Windows, Android, IOS, and web applications. The successful candidate will also provide technical guidance to our offshore validation team in India.
Requirements:
Partner with development teams to define TEST requirements, review product specifications, and align on new feature implementations.
Design and execute comprehensive TEST coverage through both manual and automated testing strategies.
Identify software vulnerabilities, edge cases, and target areas for improvement.
Detect, reproduce, and document defects across development, service, and business processes.
Manage defect tracking and documentation within Azure DevOps.
Develop, maintain, and troubleshoot automation frameworks in accordance with evolving product requirements.
Establish and refine system testing procedures and best practices.
This position is open to all candidates.
 
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Location: Caesarea
Job Type: Full Time
we are looking for a Electrical Post Silicon Validation HW Engineer.
In this role, you will be part of the Switch ASIC Post-Silicon Electrical Validation (EPSV) team.
* Ensure the ASIC operates according to specifications and reliably over time by performing extensive, high-precision measurements using advanced test equipment and procedures.
* Conduct deep-dive investigations, integrating knowledge across hardware, software, and system domains to identify root causes of observed device behavior.
* Handle all chip validation aspects, including:
* Building validation plans.
* Performing EPSV using advanced test and measurement equipment.
* Writing tests in Python over device SDK.
* Executing tests and analyzing results.
You will gain in-depth knowledge of chip architecture, functionality, and operating modes, enabling you to debug and resolve electrical chip-related issues.
Requirements:
* Bachelors degree in Electrical or Computer Engineering.
* At least 3 years of experience in hardware or post-silicon validation.
* Hands-on experience with lab equipment performing high-speed, clock, and precise voltage measurements.
* Knowledge of high-speed interfaces and high-power DC/DC design.
Preferred Qualifications
* Experience bringing up ASICs on EVBs with Board Design, FPGA, SerDes, and Software teams.
* Proficiency in debugging issues in the lab using VNA/TDR, oscilloscopes, and phase noise analyzers.
* Experience developing testing environments, performing validation activities, and analyzing data.
* Familiarity with production testing and yield improvement.
This position is open to all candidates.
 
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חברה חסויה
Location: Caesarea
Job Type: Full Time and Hybrid work
we are looking for a Senior Verification Engineer.
Your Impact
Develop advanced verification environments using SystemVerilog and UVM
Write, run, and debug testbenches to ensure complete functional coverage
Drive pre-silicon and in-lab debug activities to resolve complex issues
Collaborate with RTL, architecture, and physical design teams to achieve design closure
Support methodology development, scripting, and automation to enhance productivity
Contribute to the success, powering the next generation of Internet infrastructure
Requirements:
6+ years of experience in digital logic design verification
Advanced knowledge of SystemVerilog and UVM
Strong debug skills both pre-silicon and in-lab
Preferred Qualifications
Scripting skills (Python, Perl, TCL, or shell)
Experience with system-level integration (AMBA, PCIe, SPI, I2C, JTAG, CPU)
Basic software knowledge (driver-level)
Basic design knowledge and familiarity with CDC concepts
This position is open to all candidates.
 
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חברה חסויה
Location: Caesarea
Job Type: Full Time
We are looking for a brilliant system engineer to join us and help to scale the world of IoT.
As a system engineer, you will work on various innovative fields from RF automation, algorithms., channel usage optimizations, energy consumption optimization and dynamic network development.
Responsibilities
Design and develop algorithms and features to generate useful insight based of our Network physical signals
Research and adapt new technologies and new capabilities into our IOT network
Perform data analysis for online solution developing
Lab test and research.
Developing effective and deployable solutions to complex engineering challenges.
Detecting bottleneck problems, defining them and then come with a solution and test it before production.
Simulations and tests coding.
Requirements:
BSc. in Electrical Engineering
Strong analytical skills for algorithms definition and implementation
High level engineering orientation
Excellent understanding of statistics.
Learning capabilities and out-of-the-box thinking.
Firmware coding experience - advantage
2-3 years of experience in a similar role - advantage.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Caesarea
Job Type: Full Time and Hybrid work
we are looking for a ASIC Logic Design Engineering Technical Leader.
our Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab
Requirements:
B.Sc./M.Sc. in Electrical Engineering from a top university
​Minimum of 8 years of proven experience in a relevant field
RTL design experience
Familiarity with UVM and functional verification methodologies
Preferred Qualifications:
Experience with MATLAB simulations and bit-exact modeling environments
Familiarity with mixed-signal systems and environments
Knowledge and hands-on experience with Clock Domain Crossing (CDC)
This position is open to all candidates.
 
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חברה חסויה
Location: Caesarea
Job Type: Full Time and Hybrid work
Join the PHY system team, a pivotal part of silicon development. Our team focuses on the PHY and system aspects of our devices, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.
Key responsibilities include:
Working with the latest silicon technologies and processes to build large-scale, complex devices at the forefront of feasibility.
Contributing to the development of PHY firmware and system calibrations.
Participating in system definitions, operations, and post-silicon validation activities.
Requirements:
B.Sc/M.Sc in Electrical Engineering or Computer Science from a top university.
5+ or more years of relevant experience required
System Orientation: Strong multi-disciplinary approach with multitasking capabilities.
Major Advantage: Specialization in Communication and Signal Processing.
Experience: Hands-on experience with lab work is advantageous.
Technical Skills: Proficiency in C++, Python, and Matlab is a plus.
This position is open to all candidates.
 
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